interfisch
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7deb5b6e60
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design finished
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2023-10-11 18:18:22 +02:00 |
interfisch
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623a4e731e
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some routing done
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2023-09-27 21:50:46 +02:00 |
interfisch
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c1813fff5f
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rough placement of components
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2023-09-27 20:29:57 +02:00 |
interfisch
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be9d6091d1
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add image array code generator
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2023-09-20 19:53:32 +02:00 |
interfisch
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f2aef6201a
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add fuse footprints
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2023-09-20 19:52:40 +02:00 |
interfisch
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30aaf4e912
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add separate fuses
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2023-09-20 19:43:12 +02:00 |
interfisch
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8cffbdea92
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add test images and try slower timings for better reliability
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2023-09-20 19:22:59 +02:00 |
interfisch
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17f0de5f77
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sinus wave test
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2023-02-13 19:58:45 +01:00 |
interfisch
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aee0352422
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add third panel
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2023-02-13 19:05:24 +01:00 |
interfisch
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940d3c18cc
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fix orderarray initialization ascending
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2023-02-13 19:02:11 +01:00 |
interfisch
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5f2beca1d0
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add update order array
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2023-02-11 18:51:33 +01:00 |
interfisch
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a9711fd46d
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optimize updatebycolumn function to only flip necessary dots
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2023-02-11 18:26:52 +01:00 |
interfisch
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9ff297bd6c
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add return enum for update function
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2023-02-11 17:31:49 +01:00 |
interfisch
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5b344a6b4e
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remove row sr update when clearing
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2023-02-11 17:18:50 +01:00 |
interfisch
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fa29d3af04
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remove old code folder
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2023-02-11 14:42:44 +01:00 |
interfisch
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1dd9dc33f1
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add timing diagrams
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2023-02-11 14:41:55 +01:00 |
interfisch
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6c15882b6e
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rename pin defined to match schematic
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2023-02-11 12:17:47 +01:00 |
interfisch
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880a558951
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add random fill function
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2023-02-08 21:29:10 +01:00 |
interfisch
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3bb37dc83f
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implement basic update by column function
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2023-02-08 21:00:15 +01:00 |
interfisch
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aa14022188
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update reset wiring
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2023-02-08 20:59:27 +01:00 |
interfisch
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8b5ff04fa5
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create wrapper class for image functions
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2023-02-08 20:17:58 +01:00 |
interfisch
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b8d34ebd54
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add use of annax board shift register reset input
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2023-02-08 19:37:12 +01:00 |
interfisch
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72cfa9aa64
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connect two modules
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2023-02-07 18:37:23 +01:00 |
interfisch
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f0dda73441
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improve schematic for higher flipdot voltage
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2023-02-07 17:52:06 +01:00 |
interfisch
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fdd014012f
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move flipdot control code to class
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2023-02-07 17:51:02 +01:00 |
interfisch
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1aef191b21
|
assign footprints
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2023-02-04 01:03:47 +01:00 |
interfisch
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975a001790
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add todo comments
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2023-02-04 00:49:27 +01:00 |
interfisch
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0d2101549b
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draw current state of row driver board
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2023-02-04 00:19:25 +01:00 |
interfisch
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1350822ffe
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move flipdot functions into class
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2023-01-31 22:50:25 +01:00 |
interfisch
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7a5d35f3e1
|
clean up code
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2023-01-31 21:50:48 +01:00 |
interfisch
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387a02b37d
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fix row flipping
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2023-01-31 21:28:49 +01:00 |
interfisch
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f916bafb84
|
working clearing individual columns, problem with setting individual dots
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2023-01-25 00:18:15 +01:00 |
interfisch
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0438b4094a
|
working single column clear
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2023-01-24 23:46:52 +01:00 |
interfisch
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d41228113d
|
first success controlling the driver board with esp32
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2023-01-22 22:47:03 +01:00 |
interfisch
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8a7a669260
|
schematic fixed on data input
|
2023-01-22 22:44:46 +01:00 |
interfisch
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811bde32a0
|
start own controller implementation
|
2021-09-21 07:58:25 +02:00 |
interfisch
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c801340243
|
draw timing diagrams from platformio code
|
2020-02-14 00:02:50 +01:00 |
interfisch
|
f7f963167c
|
fix missing gnd flag
|
2020-02-01 01:04:57 +01:00 |
interfisch
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95dc7ab998
|
reorganize and fix clock pin
|
2020-01-26 22:57:09 +01:00 |
interfisch
|
1d6ba6bc48
|
cleanup wiring
|
2020-01-26 21:48:41 +01:00 |
interfisch
|
b0ed73e53c
|
fix missing connections usr
|
2020-01-26 21:39:10 +01:00 |
interfisch
|
628b477314
|
connect remaining hexinverters
|
2020-01-26 21:34:20 +01:00 |
interfisch
|
1affca3918
|
draw transistor array connections
|
2020-01-26 20:57:21 +01:00 |
interfisch
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f5d0e78f91
|
further schmematic drawing
|
2020-01-25 00:20:12 +01:00 |
interfisch
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8e7383c285
|
first few wires of reverse engineering the control pcb
|
2020-01-18 23:16:07 +01:00 |