277 lines
6.1 KiB
C
277 lines
6.1 KiB
C
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#include "../config.h"
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#include "../makros.h"
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#include <avr/interrupt.h>
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#include <avr/io.h>
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#include <avr/wdt.h>
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#include "borg_hw.h"
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/*
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// Diese #defines werden nun durch menuconfig gesetzt
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// 16 Spalten insgesamt direkt gesteuert, dafür 2 Ports
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#define COLPORT1 PORTC
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#define COLDDR1 DDRC
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#define COLPORT2 PORTA
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#define COLDDR2 DDRA
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// Der andere Port übernimmt die Steuerung der Schieberegister
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#define ROWPORT PORTD
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#define ROWDDR DDRD
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// Clock und reset gehen gemeinsam an beide Schieberegister
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// der reset pin ist negiert
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#define PIN_MCLR PD4
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#define PIN_CLK PD6
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//das dier sind die individuellen Dateneingänge für die Schieberegister
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#define PIN_DATA PD7
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*/
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//#define COLDDR1 DDR(COLPORT1)
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//#define COLDDR2 DDR(COLPORT2)
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//#define ROWDDR DDR(ROWPORT)
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//#define DATAPORT PORTC
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#define DATADDR DDR(DATAPORT)
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//#define ADDRPORT PORTA
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#define ADDRDDR DDR(ADDRPORT)
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//#define CTRLPORT PORTD
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#define CTRLDDR DDR(CTRLPORT)
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#define RDIMDDR DDR(RDIMPORT)
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//#define BIT_CS0 2
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//#define BIT_CS1 3
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//#define BIT_CS2 4
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//#define BIT_CS3 5
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//#define BIT_RW 6
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//Der Puffer, in dem das aktuelle Bild gespeichert wird
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unsigned char pixmap[NUMPLANE][NUM_ROWS][LINEBYTES];
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inline void pd1165_write(uint8_t addr, uint8_t data){
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ADDRPORT = (ADDRPORT & 0xf0) | addr;
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DATAPORT = data;
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/*
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switch (display){
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case 0:
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CTRLPORT &= ~((1<<BIT_CS0)|(1<<BIT_RW));
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CTRLPORT |= ((1<<BIT_CS0));
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break;
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case 1:
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CTRLPORT &= ~((1<<BIT_CS1)|(1<<BIT_RW));
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CTRLPORT |= ((1<<BIT_CS1));
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break;
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case 2:
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CTRLPORT &= ~((1<<BIT_CS2)|(1<<BIT_RW));
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CTRLPORT |= ((1<<BIT_CS2));
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break;
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case 3:
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CTRLPORT &= ~((1<<BIT_CS3)|(1<<BIT_RW));
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CTRLPORT |= ((1<<BIT_CS3));
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break;
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}
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*/
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}
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/*
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//Eine Zeile anzeigen
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inline void rowshow(unsigned char row, unsigned char plane){
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int addr = row;
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//Je nachdem, welche der Ebenen wir Zeichnen, die Zeile verschieden lange Anzeigen
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switch (plane){
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case 0:
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OCR0 = 3;
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break;
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case 1:
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OCR0 = 4;
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break;
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case 2:
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OCR0 = 22;
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}
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uint8_t tmp, tmp1;
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//die Daten für die aktuelle Zeile auf die Spaltentreiber ausgeben
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#ifndef INTERLACED_ROWS
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tmp = pixmap[plane][row][0];
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tmp1 = pixmap[plane][row][1];
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#else
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row = (row>>1) + ((row & 0x01)?8:0 );
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tmp = pixmap[plane][row][0];
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tmp1 = pixmap[plane][row][1];
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#endif
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#ifdef REVERSE_COLS
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tmp = (tmp >> 4) | (tmp << 4);
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tmp = ((tmp & 0xcc) >> 2) | ((tmp & 0x33)<< 2); //0xcc = 11001100, 0x33 = 00110011
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tmp = ((tmp & 0xaa) >> 1) | ((tmp & 0x55)<< 1); //0xaa = 10101010, 0x55 = 1010101
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//COLPORT2 = tmp;
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tmp = tmp1;
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tmp = (tmp >> 4) | (tmp << 4);
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tmp = ((tmp & 0xcc) >> 2) | ((tmp & 0x33) << 2); //0xcc = 11001100, 0x33 = 00110011
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tmp = ((tmp & 0xaa) >> 1) | ((tmp & 0x55) << 1); //0xaa = 10101010, 0x55 = 1010101
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//COLPORT1 = tmp;
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#else
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#ifdef INTERLACED_COLS
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static uint8_t interlace_table[16] = {
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0x00, 0x01, 0x04, 0x05, 0x10, 0x11, 0x14, 0x15, 0x40, 0x41, 0x44, 0x45, 0x50, 0x51, 0x54, 0x55
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};
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//COLPORT1 = interlace_table[tmp&0x0f] | (interlace_table[tmp1&0x0f]<<1);
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tmp>>=4; tmp1>>=4;
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//COLPORT2 = interlace_table[tmp] | (interlace_table[tmp1]<<1);
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#else
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//COLPORT1 = tmp;
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//COLPORT2 = tmp1;
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pd1165_write(row, tmp);
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#endif
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#endif
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}
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*/
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//Dieser Interrupt wird je nach Ebene mit 50kHz 31,25kHz oder 12,5kHz ausgeführt
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SIGNAL(SIG_OUTPUT_COMPARE0)
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{
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static unsigned char plane = 0;
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unsigned char row = 0;
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//Watchdog zurücksetzen
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wdt_reset();
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for(row=0; row < 8; row++){
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pd1165_write(row, pixmap[plane][row][0]);
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CTRLPORT &= ~((1<<BIT_CS3)|(1<<BIT_RW));
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CTRLPORT |= ((1<<BIT_CS3));
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pd1165_write(row, pixmap[plane][row][1]);
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CTRLPORT &= ~((1<<BIT_CS2)|(1<<BIT_RW));
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CTRLPORT |= ((1<<BIT_CS2));
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//pd1165_write(0, row, pixmap[plane][row][0]);
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//pd1165_write(1, row, pixmap[plane][row][1]);
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}
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for(row=8; row < NUM_ROWS; row++){
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pd1165_write(row-8, pixmap[plane][row][0]);
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CTRLPORT &= ~((1<<BIT_CS0)|(1<<BIT_RW));
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CTRLPORT |= ((1<<BIT_CS0));
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pd1165_write(row-8, pixmap[plane][row][1]);
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CTRLPORT &= ~((1<<BIT_CS1)|(1<<BIT_RW));
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CTRLPORT |= ((1<<BIT_CS1));
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}
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//Je nachdem, welche der Ebenen wir Zeichnen, die Zeile verschieden lange Anzeigen
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switch (plane){
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case 0:
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OCR0 = 3;
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break;
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case 1:
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OCR0 = 4;
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break;
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case 2:
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OCR0 = 22;
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}
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//Zeile und Ebene inkrementieren
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if(++plane==NUMPLANE){
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plane=0;
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}
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}
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void timer0_off(){
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cli();
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TCCR0 = 0x00;
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sei();
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}
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// Den Timer, der denn Interrupt auslöst, initialisieren
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void timer0_on(){
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/* TCCR0: FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00
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CS02 CS01 CS00
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0 0 0 stop
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0 0 1 clk
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0 1 0 clk/8
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0 1 1 clk/64
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1 0 0 clk/256
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1 0 1 clk/1024
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*/
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TCCR0 = 0x0D; // CTC Mode, clk/64
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TCNT0 = 0; // reset timer
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OCR0 = 20; // Compare with this value
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TIMSK = 0x02; // Compare match Interrupt on
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}
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void timer2_on(){
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/* TCCR2: FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20
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CS02 CS01 CS00
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0 0 0 stop
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0 0 1 clk
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0 1 0 clk/8
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0 1 1 clk/32
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1 0 0 clk/64
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1 0 1 clk/128
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1 1 0 clk/256
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1 1 1 clk/1024
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Table 51. Compare Output Mode, non-PWM Mode
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COM21 COM20 Description
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0 0 Normal port operation, OC2 disconnected.
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0 1 Toggle OC2 on compare match
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1 0 Clear OC2 on compare match
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1 1 Set OC2 on compare match
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*/
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TCCR2 = (1<<WGM21) | (1<<COM20) | 1 ; //CTC, OC2 toggle, clk/1
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OCR2 = 100; //80kHz clock on OC2
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}
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void borg_hw_init(){
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CTRLDDR = (1<<BIT_CS0)|(1<<BIT_CS1)|(1<<BIT_CS2)|(1<<BIT_CS3)|(1<<BIT_RW);
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CTRLPORT = (1<<BIT_CS0)|(1<<BIT_CS1)|(1<<BIT_CS2)|(1<<BIT_CS3)|(1<<BIT_RW);
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DATADDR = 0xff;
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ADDRDDR |= 0x0f;
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CTRLPORT = (1<<BIT_CS0)|(1<<BIT_CS1)|(1<<BIT_CS2)|(1<<BIT_CS3)|(1<<BIT_RW);
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pd1165_write(8, 0x10 | 7);
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CTRLPORT &= ~((1<<BIT_CS0)|(1<<BIT_CS1)|(1<<BIT_CS2)|(1<<BIT_CS3)|(1<<BIT_RW));
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CTRLPORT |= ((1<<BIT_CS0)|(1<<BIT_CS1)|(1<<BIT_CS2)|(1<<BIT_CS3));
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timer0_on();
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timer2_on();
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DDRD |= 1<<PD7; //OC2 pin to output
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RDIMPORT |= (1<<BIT_RDIM);
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RDIMDDR |= (1<<BIT_RDIM);
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//Watchdog Timer aktivieren
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wdt_reset();
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wdt_enable(0x00); // 17ms Watchdog
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}
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