2011-05-08 20:58:56 +00:00
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#include "../config.h"
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#include "../makros.h"
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#include "../ioport.h"
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#include <avr/interrupt.h>
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#include <avr/io.h>
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#include <avr/wdt.h>
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#include "borg_hw.h"
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2011-08-17 01:16:25 +00:00
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// buffer which holds the currently shown frame
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2011-05-08 20:58:56 +00:00
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unsigned char pixmap[NUMPLANE][NUM_ROWS][LINEBYTES];
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2011-08-17 01:16:25 +00:00
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// display a row
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inline void rowshow(unsigned char row) {
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// output data of the current row to the column drivers
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COLPORT1 = pixmap[0][row][0];
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COLPORT2 = pixmap[0][row][1];
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2011-05-08 20:58:56 +00:00
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OUTPUT_ON(LATCH_R);
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OUTPUT_OFF(LATCH_R);
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2011-08-17 01:16:25 +00:00
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COLPORT1 = pixmap[1][row][0];
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COLPORT2 = pixmap[1][row][1];
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2011-05-08 20:58:56 +00:00
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OUTPUT_ON(LATCH_G);
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OUTPUT_OFF(LATCH_G);
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2011-08-17 01:16:25 +00:00
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COLPORT1 = pixmap[2][row][0];
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COLPORT2 = pixmap[2][row][1];
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2011-05-08 20:58:56 +00:00
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OUTPUT_ON(LATCH_B);
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OUTPUT_OFF(LATCH_B);
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}
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uint32_t mod = 1280000ul;
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uint32_t akku;
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unsigned char row = 0;
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2011-08-17 01:16:25 +00:00
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2011-05-08 20:58:56 +00:00
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ISR(SIG_OUTPUT_COMPARE0)
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{
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2011-08-17 01:16:25 +00:00
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// reset watchdog
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2011-05-08 20:58:56 +00:00
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wdt_reset();
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2011-08-17 01:16:25 +00:00
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2011-05-08 20:58:56 +00:00
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akku += mod;
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2011-08-17 01:16:25 +00:00
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2011-05-08 20:58:56 +00:00
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OCR1A = akku / 256;
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rowshow(row);
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2011-08-17 01:16:25 +00:00
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if (++row == NUM_ROWS) {
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2011-05-08 20:58:56 +00:00
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row = NUM_ROWS - 1;
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}
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}
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2011-08-17 01:16:25 +00:00
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ISR(INT0_vect) {
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if (akku > (64ul * 256ul * 64ul)) {
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2011-05-08 20:58:56 +00:00
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akku -= OCR1A - TCNT1;
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2011-08-17 01:16:25 +00:00
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2011-05-08 20:58:56 +00:00
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mod = akku / 64;
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akku = 0;
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row = 0;
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OCR1A = 0;
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TCNT1 = 0xffff;
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}
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}
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2011-08-17 01:16:25 +00:00
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void timer0_off() {
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2011-05-08 20:58:56 +00:00
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cli();
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TCCR1B = 0x00;
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sei();
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}
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2011-08-17 01:16:25 +00:00
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// initialize timer which triggers the interrupt
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void timer1_on() {
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TCCR1B = 1; // clk/1
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TIMSK |= (1 << OCIE1A);
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2011-05-08 20:58:56 +00:00
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}
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2011-08-17 01:16:25 +00:00
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void borg_hw_init() {
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2011-05-08 20:58:56 +00:00
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DDR(COLPORT1) = 0xff;
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DDR(COLPORT2) = 0xff;
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2011-08-17 01:16:25 +00:00
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2011-05-08 20:58:56 +00:00
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SET_DDR(LATCH_R);
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SET_DDR(LATCH_G);
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SET_DDR(LATCH_B);
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2011-08-17 01:16:25 +00:00
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2011-05-08 20:58:56 +00:00
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timer1_on();
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2011-08-17 01:16:25 +00:00
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// activate watchdog timer
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2011-05-08 20:58:56 +00:00
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wdt_reset();
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2011-08-17 01:16:25 +00:00
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wdt_enable(0x00); // 17ms watchdog
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2011-05-08 20:58:56 +00:00
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}
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