581 lines
11 KiB
C
581 lines
11 KiB
C
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#include <stdlib.h>
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#include "defs.h"
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#include "hw.h"
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#include "regs.h"
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#include "mem.h"
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#include "rtc.h"
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#include "lcd.h"
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struct mbc mbc;
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struct rom rom;
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struct ram ram;
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/*
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* In order to make reads and writes efficient, we keep tables
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* (indexed by the high nibble of the address) specifying which
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* regions can be read/written without a function call. For such
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* ranges, the pointer in the map table points to the base of the
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* region in host system memory. For ranges that require special
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* processing, the pointer is NULL.
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*
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* mem_updatemap is called whenever bank changes or other operations
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* make the old maps potentially invalid.
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*/
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void mem_updatemap()
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{
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int n;
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byte **map;
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mbc.rombank &= (mbc.romsize - 1);
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mbc.rambank &= (mbc.ramsize - 1);
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map = mbc.rmap;
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map[0x0] = rom.bank[0];
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map[0x1] = rom.bank[0];
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map[0x2] = rom.bank[0];
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map[0x3] = rom.bank[0];
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if (mbc.rombank < mbc.romsize)
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{
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map[0x4] = rom.bank[mbc.rombank] - 0x4000;
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map[0x5] = rom.bank[mbc.rombank] - 0x4000;
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map[0x6] = rom.bank[mbc.rombank] - 0x4000;
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map[0x7] = rom.bank[mbc.rombank] - 0x4000;
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}
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else map[0x4] = map[0x5] = map[0x6] = map[0x7] = NULL;
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if (0 && (R_STAT & 0x03) == 0x03)
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{
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map[0x8] = NULL;
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map[0x9] = NULL;
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}
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else
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{
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map[0x8] = lcd.vbank[R_VBK & 1] - 0x8000;
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map[0x9] = lcd.vbank[R_VBK & 1] - 0x8000;
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}
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if (mbc.enableram && !(rtc.sel&8))
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{
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map[0xA] = ram.sbank[mbc.rambank] - 0xA000;
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map[0xB] = ram.sbank[mbc.rambank] - 0xA000;
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}
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else map[0xA] = map[0xB] = NULL;
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map[0xC] = ram.ibank[0] - 0xC000;
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n = R_SVBK & 0x07;
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map[0xD] = ram.ibank[n?n:1] - 0xD000;
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map[0xE] = ram.ibank[0] - 0xE000;
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map[0xF] = NULL;
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map = mbc.wmap;
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map[0x0] = map[0x1] = map[0x2] = map[0x3] = NULL;
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map[0x4] = map[0x5] = map[0x6] = map[0x7] = NULL;
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map[0x8] = map[0x9] = NULL;
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if (mbc.enableram && !(rtc.sel&8))
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{
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map[0xA] = ram.sbank[mbc.rambank] - 0xA000;
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map[0xB] = ram.sbank[mbc.rambank] - 0xA000;
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}
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else map[0xA] = map[0xB] = NULL;
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map[0xC] = ram.ibank[0] - 0xC000;
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n = R_SVBK & 0x07;
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map[0xD] = ram.ibank[n?n:1] - 0xD000;
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map[0xE] = ram.ibank[0] - 0xE000;
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map[0xF] = NULL;
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}
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/*
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* ioreg_write handles output to io registers in the FF00-FF7F,FFFF
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* range. It takes the register number (low byte of the address) and a
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* byte value to be written.
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*/
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void ioreg_write(byte r, byte b)
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{
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if (!hw.cgb)
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{
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switch (r)
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{
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case RI_VBK:
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case RI_BCPS:
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case RI_OCPS:
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case RI_BCPD:
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case RI_OCPD:
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case RI_SVBK:
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case RI_KEY1:
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case RI_HDMA1:
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case RI_HDMA2:
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case RI_HDMA3:
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case RI_HDMA4:
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case RI_HDMA5:
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return;
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}
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}
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switch(r)
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{
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case RI_TIMA:
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case RI_TMA:
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case RI_TAC:
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case RI_SCY:
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case RI_SCX:
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case RI_WY:
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case RI_WX:
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REG(r) = b;
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break;
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case RI_BGP:
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if (R_BGP == b) break;
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pal_write_dmg(0, 0, b);
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pal_write_dmg(8, 1, b);
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R_BGP = b;
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break;
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case RI_OBP0:
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if (R_OBP0 == b) break;
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pal_write_dmg(64, 2, b);
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R_OBP0 = b;
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break;
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case RI_OBP1:
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if (R_OBP1 == b) break;
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pal_write_dmg(72, 3, b);
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R_OBP1 = b;
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break;
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case RI_IF:
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case RI_IE:
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REG(r) = b & 0x1F;
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break;
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case RI_P1:
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REG(r) = b;
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pad_refresh();
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break;
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case RI_SC:
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/* FIXME - this is a hack for stupid roms that probe serial */
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if ((b & 0x81) == 0x81)
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{
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R_SB = 0xff;
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hw_interrupt(IF_SERIAL, IF_SERIAL);
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hw_interrupt(0, IF_SERIAL);
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}
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R_SC = b; /* & 0x7f; */
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break;
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case RI_SB:
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REG(r) = b;
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break;
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case RI_DIV:
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REG(r) = 0;
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break;
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case RI_LCDC:
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lcdc_change(b);
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break;
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case RI_STAT:
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stat_write(b);
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break;
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case RI_LYC:
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REG(r) = b;
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stat_trigger();
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break;
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case RI_VBK:
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REG(r) = b | 0xFE;
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mem_updatemap();
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break;
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case RI_BCPS:
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R_BCPS = b & 0xBF;
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R_BCPD = lcd.pal[b & 0x3F];
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break;
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case RI_OCPS:
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R_OCPS = b & 0xBF;
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R_OCPD = lcd.pal[64 + (b & 0x3F)];
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break;
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case RI_BCPD:
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R_BCPD = b;
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pal_write(R_BCPS & 0x3F, b);
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if (R_BCPS & 0x80) R_BCPS = (R_BCPS+1) & 0xBF;
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break;
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case RI_OCPD:
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R_OCPD = b;
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pal_write(64 + (R_OCPS & 0x3F), b);
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if (R_OCPS & 0x80) R_OCPS = (R_OCPS+1) & 0xBF;
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break;
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case RI_SVBK:
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REG(r) = b & 0x07;
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mem_updatemap();
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break;
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case RI_DMA:
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hw_dma(b);
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break;
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case RI_KEY1:
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REG(r) = (REG(r) & 0x80) | (b & 0x01);
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break;
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case RI_HDMA1:
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REG(r) = b;
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break;
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case RI_HDMA2:
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REG(r) = b & 0xF0;
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break;
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case RI_HDMA3:
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REG(r) = b & 0x1F;
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break;
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case RI_HDMA4:
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REG(r) = b & 0xF0;
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break;
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case RI_HDMA5:
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hw_hdma_cmd(b);
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break;
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}
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switch (r)
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{
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case RI_BGP:
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case RI_OBP0:
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case RI_OBP1:
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/* printf("palette reg %02X write %02X at LY=%02X\n", r, b, R_LY); */
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case RI_HDMA1:
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case RI_HDMA2:
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case RI_HDMA3:
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case RI_HDMA4:
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case RI_HDMA5:
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/* printf("HDMA %d: %02X\n", r - RI_HDMA1 + 1, b); */
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break;
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}
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/* printf("reg %02X => %02X (%02X)\n", r, REG(r), b); */
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}
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byte ioreg_read(byte r)
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{
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switch(r)
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{
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case RI_SC:
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r = R_SC;
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R_SC &= 0x7f;
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return r;
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case RI_P1:
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case RI_SB:
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case RI_DIV:
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case RI_TIMA:
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case RI_TMA:
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case RI_TAC:
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case RI_LCDC:
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case RI_STAT:
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case RI_SCY:
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case RI_SCX:
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case RI_LY:
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case RI_LYC:
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case RI_BGP:
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case RI_OBP0:
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case RI_OBP1:
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case RI_WY:
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case RI_WX:
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case RI_IE:
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case RI_IF:
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return REG(r);
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case RI_VBK:
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case RI_BCPS:
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case RI_OCPS:
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case RI_BCPD:
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case RI_OCPD:
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case RI_SVBK:
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case RI_KEY1:
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case RI_HDMA1:
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case RI_HDMA2:
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case RI_HDMA3:
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case RI_HDMA4:
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case RI_HDMA5:
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if (hw.cgb) return REG(r);
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default:
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return 0xff;
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}
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}
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/*
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* Memory bank controllers typically intercept write attempts to
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* 0000-7FFF, using the address and byte written as instructions to
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* change rom or sram banks, control special hardware, etc.
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*
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* mbc_write takes an address (which should be in the proper range)
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* and a byte value written to the address.
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*/
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void mbc_write(int a, byte b)
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{
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byte ha = (a>>12);
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/* printf("mbc %d: rom bank %02X -[%04X:%02X]-> ", mbc.type, mbc.rombank, a, b); */
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switch (mbc.type)
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{
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case MBC_MBC1:
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switch (ha & 0xE)
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{
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case 0x0:
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mbc.enableram = ((b & 0x0F) == 0x0A);
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break;
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case 0x2:
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if ((b & 0x1F) == 0) b = 0x01;
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mbc.rombank = (mbc.rombank & 0x60) | (b & 0x1F);
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break;
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case 0x4:
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if (mbc.model)
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{
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mbc.rambank = b & 0x03;
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break;
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}
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mbc.rombank = (mbc.rombank & 0x1F) | ((int)(b&3)<<5);
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break;
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case 0x6:
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mbc.model = b & 0x1;
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break;
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}
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break;
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case MBC_MBC2: /* is this at all right? */
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if ((a & 0x0100) == 0x0000)
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{
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mbc.enableram = ((b & 0x0F) == 0x0A);
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break;
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}
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if ((a & 0xE100) == 0x2100)
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{
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mbc.rombank = b & 0x0F;
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break;
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}
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break;
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case MBC_MBC3:
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switch (ha & 0xE)
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{
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case 0x0:
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mbc.enableram = ((b & 0x0F) == 0x0A);
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break;
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case 0x2:
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if ((b & 0x7F) == 0) b = 0x01;
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mbc.rombank = b & 0x7F;
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break;
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case 0x4:
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rtc.sel = b & 0x0f;
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mbc.rambank = b & 0x03;
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break;
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case 0x6:
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rtc_latch(b);
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break;
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}
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break;
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case MBC_RUMBLE:
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switch (ha & 0xF)
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{
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case 0x4:
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case 0x5:
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/* FIXME - save high bit as rumble state */
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/* mask off high bit */
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b &= 0x7;
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break;
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}
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/* fall thru */
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case MBC_MBC5:
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switch (ha & 0xF)
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{
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case 0x0:
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case 0x1:
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mbc.enableram = ((b & 0x0F) == 0x0A);
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break;
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case 0x2:
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if ((b & 0xFF) == 0) b = 0x01;
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mbc.rombank = (mbc.rombank & 0x100) | (b & 0xFF);
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break;
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case 0x3:
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mbc.rombank = (mbc.rombank & 0xFF) | ((int)(b&1)<<8);
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break;
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case 0x4:
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case 0x5:
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mbc.rambank = b & 0x0f;
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break;
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}
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break;
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case MBC_HUC1: /* FIXME - this is all guesswork -- is it right??? */
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switch (ha & 0xE)
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{
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case 0x0:
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mbc.enableram = ((b & 0x0F) == 0x0A);
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break;
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case 0x2:
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if ((b & 0x1F) == 0) b = 0x01;
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mbc.rombank = (mbc.rombank & 0x60) | (b & 0x1F);
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break;
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case 0x4:
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if (mbc.model)
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{
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mbc.rambank = b & 0x03;
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break;
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}
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mbc.rombank = (mbc.rombank & 0x1F) | ((int)(b&3)<<5);
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break;
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case 0x6:
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mbc.model = b & 0x1;
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break;
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}
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break;
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case MBC_HUC3:
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switch (ha & 0xE)
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{
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case 0x0:
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mbc.enableram = ((b & 0x0F) == 0x0A);
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break;
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case 0x2:
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b &= 0x7F;
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mbc.rombank = b ? b : 1;
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break;
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case 0x4:
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rtc.sel = b & 0x0f;
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mbc.rambank = b & 0x03;
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break;
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case 0x6:
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rtc_latch(b);
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break;
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}
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break;
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}
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/* printf("%02X\n", mbc.rombank); */
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mem_updatemap();
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}
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/*
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* mem_write is the basic write function. Although it should only be
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* called when the write map contains a NULL for the requested address
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* region, it accepts writes to any address.
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*/
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void mem_write(int a, byte b)
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{
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int n;
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byte ha = (a>>12) & 0xE;
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/* printf("write to 0x%04X: 0x%02X\n", a, b); */
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switch (ha)
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{
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case 0x0:
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case 0x2:
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case 0x4:
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case 0x6:
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mbc_write(a, b);
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break;
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case 0x8:
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/* if ((R_STAT & 0x03) == 0x03) break; */
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vram_write(a & 0x1FFF, b);
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break;
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case 0xA:
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if (!mbc.enableram) break;
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if (rtc.sel&8)
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{
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rtc_write(b);
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break;
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}
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ram.sbank[mbc.rambank][a & 0x1FFF] = b;
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break;
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case 0xC:
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if ((a & 0xF000) == 0xC000)
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{
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ram.ibank[0][a & 0x0FFF] = b;
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break;
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}
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n = R_SVBK & 0x07;
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ram.ibank[n?n:1][a & 0x0FFF] = b;
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break;
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case 0xE:
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if (a < 0xFE00)
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{
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mem_write(a & 0xDFFF, b);
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break;
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}
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if ((a & 0xFF00) == 0xFE00)
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{
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/* if (R_STAT & 0x02) break; */
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if (a < 0xFEA0) lcd.oam.mem[a & 0xFF] = b;
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break;
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}
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/* return writehi(a & 0xFF, b); */
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if (a >= 0xFF10 && a <= 0xFF3F)
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{
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sound_write(a & 0xFF, b);
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break;
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}
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if ((a & 0xFF80) == 0xFF80 && a != 0xFFFF)
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{
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ram.hi[a & 0xFF] = b;
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break;
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}
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ioreg_write(a & 0xFF, b);
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}
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}
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/*
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* mem_read is the basic read function...not useful for much anymore
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* with the read map, but it's still necessary for the final messy
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* region.
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*/
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byte mem_read(int a)
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{
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int n;
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byte ha = (a>>12) & 0xE;
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|
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/* printf("read %04x\n", a); */
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switch (ha)
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{
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case 0x0:
|
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case 0x2:
|
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return rom.bank[0][a];
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case 0x4:
|
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case 0x6:
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return rom.bank[mbc.rombank][a & 0x3FFF];
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case 0x8:
|
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/* if ((R_STAT & 0x03) == 0x03) return 0xFF; */
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return lcd.vbank[R_VBK&1][a & 0x1FFF];
|
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case 0xA:
|
|
if (!mbc.enableram && mbc.type == MBC_HUC3)
|
|
return 0x01;
|
|
if (!mbc.enableram)
|
|
return 0xFF;
|
|
if (rtc.sel&8)
|
|
return rtc.regs[rtc.sel&7];
|
|
return ram.sbank[mbc.rambank][a & 0x1FFF];
|
|
case 0xC:
|
|
if ((a & 0xF000) == 0xC000)
|
|
return ram.ibank[0][a & 0x0FFF];
|
|
n = R_SVBK & 0x07;
|
|
return ram.ibank[n?n:1][a & 0x0FFF];
|
|
case 0xE:
|
|
if (a < 0xFE00) return mem_read(a & 0xDFFF);
|
|
if ((a & 0xFF00) == 0xFE00)
|
|
{
|
|
/* if (R_STAT & 0x02) return 0xFF; */
|
|
if (a < 0xFEA0) return lcd.oam.mem[a & 0xFF];
|
|
return 0xFF;
|
|
}
|
|
/* return readhi(a & 0xFF); */
|
|
if (a == 0xFFFF) return REG(0xFF);
|
|
if (a >= 0xFF10 && a <= 0xFF3F)
|
|
return sound_read(a & 0xFF);
|
|
if ((a & 0xFF80) == 0xFF80)
|
|
return ram.hi[a & 0xFF];
|
|
return ioreg_read(a & 0xFF);
|
|
}
|
|
return 0xff; /* not reached */
|
|
}
|
|
|
|
void mbc_reset()
|
|
{
|
|
mbc.rombank = 1;
|
|
mbc.rambank = 0;
|
|
mbc.enableram = 0;
|
|
mem_updatemap();
|
|
}
|
|
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