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start schematic with teensy footprint and symbol

This commit is contained in:
interfisch 2022-03-28 22:09:25 +02:00
parent 8d1c0fb99e
commit aa8570af42
9 changed files with 709 additions and 0 deletions
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6
.gitmodules vendored
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@ -13,3 +13,9 @@
[submodule "hoverbrettctrl/lib/hoverboard-esc-serial-comm"]
path = hoverbrettctrl/lib/hoverboard-esc-serial-comm
url = https://repos.ctdo.de/interfisch/hoverboard-esc-serial-comm
[submodule "hardware/controller/teensy_library"]
path = hardware/controller/teensy_library
url = https://github.com/XenGi/teensy_library
[submodule "hardware/controller/teensy.pretty"]
path = hardware/controller/teensy.pretty
url = https://github.com/XenGi/teensy.pretty

29
hardware/controller/.gitignore vendored Normal file
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@ -0,0 +1,29 @@
# For PCBs designed using KiCad: https://www.kicad.org/
# Format documentation: https://kicad.org/help/file-formats/
# Temporary files
*.000
*.bak
*.bck
*.kicad_pcb-bak
*.kicad_sch-bak
*-backups
*.kicad_prl
*.sch-bak
*~
_autosave-*
*.tmp
*-save.pro
*-save.kicad_pcb
fp-info-cache
# Netlist files (exported from Eeschema)
*.net
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
# Exported BOM files
*.xml
*.csv

2
hardware/controller/controller.kicad_pcb Normal file
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@ -0,0 +1,2 @@
(kicad_pcb (version 20211014) (generator pcbnew)
)

326
hardware/controller/controller.kicad_pro Normal file
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@ -0,0 +1,326 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"min_copper_edge_clearance": 0.0,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
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],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "controller.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
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"drawing": {
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"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
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},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"e63e39d7-6ac0-4ffd-8aa3-1841a4541b55",
""
]
],
"text_variables": {}
}

337
hardware/controller/controller.kicad_sch Normal file
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@ -0,0 +1,337 @@
(kicad_sch (version 20211123) (generator eeschema)
(uuid e63e39d7-6ac0-4ffd-8aa3-1841a4541b55)
(paper "A4")
(lib_symbols
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)
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(effects (font (size 1.27 1.27)))
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)
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(rectangle (start -20.32 -36.83) (end 20.32 36.83)
(stroke (width 0) (type default) (color 0 0 0 0))
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)
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4
hardware/controller/fp-lib-table Normal file
View File

@ -0,0 +1,4 @@
(fp_lib_table
(lib (name "teensy 3.2 all")(type "KiCad")(uri "${KIPRJMOD}/teensy.pretty/Teensy30_31_32_All_Pins.kicad_mod")(options "")(descr ""))
(lib (name "teensy 3.2 lc")(type "KiCad")(uri "${KIPRJMOD}/teensy.pretty/Teensy30_31_32_LC.kicad_mod")(options "")(descr ""))
)

3
hardware/controller/sym-lib-table Normal file
View File

@ -0,0 +1,3 @@
(sym_lib_table
(lib (name "Teensy")(type "Legacy")(uri "${KIPRJMOD}/teensy_library/teensy.lib")(options "")(descr ""))
)

1
hardware/controller/teensy.pretty Submodule

@ -0,0 +1 @@
Subproject commit ab50abcedbe69716f4f3d0925abb24e38a32a332

1
hardware/controller/teensy_library Submodule

@ -0,0 +1 @@
Subproject commit 6f0ed76aa1e392bf9a35a5e5e51ecb9f598c4f37