diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..e3e7585 --- /dev/null +++ b/.clang-format @@ -0,0 +1,27 @@ +--- +BasedOnStyle: LLVM +AccessModifierOffset: '2' +AlignAfterOpenBracket: Align +AlignConsecutiveAssignments: 'true' +AlignOperands: 'false' +AlignTrailingComments: 'true' +SortIncludes: 'false' +ColumnLimit: '0' +IndentCaseLabels: 'true' +IndentWidth: '2' +KeepEmptyLinesAtTheStartOfBlocks: 'false' +MaxEmptyLinesToKeep: '2' +SpaceAfterCStyleCast: 'false' +SpaceBeforeAssignmentOperators: 'true' +SpaceBeforeParens: Never +SpaceInEmptyParentheses: 'false' +SpacesBeforeTrailingComments: '2' +SpacesInAngles: 'false' +SpacesInCStyleCastParentheses: 'false' +SpacesInContainerLiterals: 'false' +SpacesInParentheses: 'false' +SpacesInSquareBrackets: 'false' +TabWidth: '2' +UseTab: Never + +... diff --git a/Inc/stm32f1xx_hal_conf.h b/Inc/stm32f1xx_hal_conf.h index cc6eb3b..1f0f896 100644 --- a/Inc/stm32f1xx_hal_conf.h +++ b/Inc/stm32f1xx_hal_conf.h @@ -30,14 +30,14 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_CONF_H #define __STM32F1xx_HAL_CONF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -47,8 +47,8 @@ /** * @brief This is the list of modules to be used in the HAL driver */ - -#define HAL_MODULE_ENABLED + +#define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED /*#define HAL_CRYP_MODULE_ENABLED */ /*#define HAL_CAN_MODULE_ENABLED */ @@ -96,12 +96,12 @@ * This value is used by the RCC HAL module to compute the system frequency * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#if !defined(HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ +#if !defined(HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -109,29 +109,29 @@ * This value is used by the RCC HAL module to compute the system frequency * (when HSI is used as system clock source, directly or through the PLL). */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +#if !defined(HSI_VALUE) +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ +#if !defined(LSI_VALUE) +#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz \ + The real value may vary depending on the variations \ + in voltage and temperature. */ /** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ +#if !defined(LSE_VALUE) +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ #endif /* LSE_VALUE */ -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ +#if !defined(LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -140,11 +140,11 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 1 + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 /* ########################## Assert Selection ############################## */ /** @@ -158,56 +158,56 @@ /* Section 1 : Ethernet peripheral configuration */ /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2 -#define MAC_ADDR1 0 -#define MAC_ADDR2 0 -#define MAC_ADDR3 0 -#define MAC_ADDR4 0 -#define MAC_ADDR5 0 +#define MAC_ADDR0 2 +#define MAC_ADDR1 0 +#define MAC_ADDR2 0 +#define MAC_ADDR3 0 +#define MAC_ADDR4 0 +#define MAC_ADDR5 0 -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ /* Section 2: PHY configuration section */ -/* DP83848_PHY_ADDRESS Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FF) +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FF) /* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) -#define PHY_READ_TO ((uint32_t)0x0000FFFF) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) +#define PHY_READ_TO ((uint32_t)0x0000FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) /* Section 3: Common PHY Registers */ -#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ +#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - /* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ /* Includes ------------------------------------------------------------------*/ /** @@ -215,132 +215,132 @@ */ #ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f1xx_hal_rcc.h" +#include "stm32f1xx_hal_rcc.h" #endif /* HAL_RCC_MODULE_ENABLED */ #ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f1xx_hal_gpio.h" +#include "stm32f1xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ - + #ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f1xx_hal_dma.h" +#include "stm32f1xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f1xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - +#include "stm32f1xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + #ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f1xx_hal_can.h" +#include "stm32f1xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ #ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f1xx_hal_cec.h" +#include "stm32f1xx_hal_cec.h" #endif /* HAL_CEC_MODULE_ENABLED */ #ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f1xx_hal_cortex.h" +#include "stm32f1xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ #ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f1xx_hal_adc.h" +#include "stm32f1xx_hal_adc.h" #endif /* HAL_ADC_MODULE_ENABLED */ #ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f1xx_hal_crc.h" +#include "stm32f1xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f1xx_hal_dac.h" +#include "stm32f1xx_hal_dac.h" #endif /* HAL_DAC_MODULE_ENABLED */ #ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f1xx_hal_flash.h" +#include "stm32f1xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ #ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f1xx_hal_sram.h" +#include "stm32f1xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ #ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f1xx_hal_nor.h" +#include "stm32f1xx_hal_nor.h" #endif /* HAL_NOR_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f1xx_hal_i2c.h" +#include "stm32f1xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ #ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f1xx_hal_i2s.h" +#include "stm32f1xx_hal_i2s.h" #endif /* HAL_I2S_MODULE_ENABLED */ #ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f1xx_hal_iwdg.h" +#include "stm32f1xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f1xx_hal_pwr.h" +#include "stm32f1xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ #ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f1xx_hal_rtc.h" +#include "stm32f1xx_hal_rtc.h" #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f1xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ +#include "stm32f1xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ #ifdef HAL_SD_MODULE_ENABLED - #include "stm32f1xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ +#include "stm32f1xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ #ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f1xx_hal_mmc.h" +#include "stm32f1xx_hal_mmc.h" #endif /* HAL_MMC_MODULE_ENABLED */ #ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f1xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ +#include "stm32f1xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f1xx_hal_spi.h" +#include "stm32f1xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ #ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f1xx_hal_tim.h" +#include "stm32f1xx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ #ifdef HAL_UART_MODULE_ENABLED - #include "stm32f1xx_hal_uart.h" +#include "stm32f1xx_hal_uart.h" #endif /* HAL_UART_MODULE_ENABLED */ #ifdef HAL_USART_MODULE_ENABLED - #include "stm32f1xx_hal_usart.h" +#include "stm32f1xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ #ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f1xx_hal_irda.h" +#include "stm32f1xx_hal_irda.h" #endif /* HAL_IRDA_MODULE_ENABLED */ #ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f1xx_hal_smartcard.h" +#include "stm32f1xx_hal_smartcard.h" #endif /* HAL_SMARTCARD_MODULE_ENABLED */ #ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f1xx_hal_wwdg.h" +#include "stm32f1xx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ #ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f1xx_hal_pcd.h" +#include "stm32f1xx_hal_pcd.h" #endif /* HAL_PCD_MODULE_ENABLED */ #ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f1xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - +#include "stm32f1xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function @@ -349,11 +349,11 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); +void assert_failed(uint8_t *file, uint32_t line); #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ #ifdef __cplusplus diff --git a/Inc/stm32f1xx_it.h b/Inc/stm32f1xx_it.h index dcbfccc..237a392 100644 --- a/Inc/stm32f1xx_it.h +++ b/Inc/stm32f1xx_it.h @@ -36,8 +36,8 @@ #define __STM32F1xx_IT_H #ifdef __cplusplus - extern "C" { -#endif +extern "C" { +#endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" diff --git a/Makefile b/Makefile index f46c84f..232a093 100644 --- a/Makefile +++ b/Makefile @@ -149,6 +149,8 @@ $(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) $(BUILD_DIR): mkdir $@ +format: + find Src/ Inc/ -iname '*.h' -o -iname '*.c' | xargs clang-format -i ####################################### # clean up ####################################### diff --git a/Src/main.c b/Src/main.c index 6801b51..203de1e 100644 --- a/Src/main.c +++ b/Src/main.c @@ -38,18 +38,18 @@ volatile int pwmr = 0; const int pwm_res = 64000000 / 2 / PWM_FREQ; const uint8_t hall_to_pos[8] = { - 0, - 0, - 2, - 1, - 4, - 5, - 3, - 0, + 0, + 0, + 2, + 1, + 4, + 5, + 3, + 0, }; -inline void block(int pwm, int pos, int* u, int* v, int* w){ - switch(pos){ +inline void block(int pwm, int pos, int *u, int *v, int *w) { + switch(pos) { case 0: *u = 0; *v = pwm; @@ -87,16 +87,16 @@ inline void block(int pwm, int pos, int* u, int* v, int* w){ } } -int last_pos = 0; -int timer = 0; -int max_time = PWM_FREQ / 10; +int last_pos = 0; +int timer = 0; +int max_time = PWM_FREQ / 10; volatile int vel = 0; volatile uint8_t uart_buf[10]; -void DMA1_Channel1_IRQHandler(){ +void DMA1_Channel1_IRQHandler() { DMA1->IFCR = DMA_IFCR_CTCIF1; - + HAL_GPIO_WritePin(LED_PORT, LED_PIN, 1); /* uart_buf[0] = 0xff; uart_buf[1] = adc_buffer.r_dc1 - 1850 + 127; @@ -117,17 +117,15 @@ void DMA1_Channel1_IRQHandler(){ } */ - if(adc_buffer.l_dc2 > 1950){ + if(adc_buffer.l_dc2 > 1950) { LEFT_TIM->BDTR &= ~TIM_BDTR_MOE; - HAL_GPIO_WritePin(LED_PORT, LED_PIN, 1); - }else{ + } else { LEFT_TIM->BDTR |= TIM_BDTR_MOE; - HAL_GPIO_WritePin(LED_PORT, LED_PIN, 0); } - if(adc_buffer.r_dc1 > 1950){ + if(adc_buffer.r_dc1 > 1950) { RIGHT_TIM->BDTR &= ~TIM_BDTR_MOE; - }else{ + } else { RIGHT_TIM->BDTR |= TIM_BDTR_MOE; } @@ -139,21 +137,21 @@ void DMA1_Channel1_IRQHandler(){ int vr = 0; int wr = 0; - uint8_t hall_ul = HAL_GPIO_ReadPin(LEFT_HALL_U_PORT, LEFT_HALL_U_PIN); - uint8_t hall_vl = HAL_GPIO_ReadPin(LEFT_HALL_V_PORT, LEFT_HALL_V_PIN); - uint8_t hall_wl = HAL_GPIO_ReadPin(LEFT_HALL_W_PORT, LEFT_HALL_W_PIN); + uint8_t hall_ul = !(LEFT_HALL_U_PORT->IDR & LEFT_HALL_U_PIN); + uint8_t hall_vl = !(LEFT_HALL_V_PORT->IDR & LEFT_HALL_V_PIN); + uint8_t hall_wl = !(LEFT_HALL_W_PORT->IDR & LEFT_HALL_W_PIN); - uint8_t hall_ur = HAL_GPIO_ReadPin(RIGHT_HALL_U_PORT, RIGHT_HALL_U_PIN); - uint8_t hall_vr = HAL_GPIO_ReadPin(RIGHT_HALL_V_PORT, RIGHT_HALL_V_PIN); - uint8_t hall_wr = HAL_GPIO_ReadPin(RIGHT_HALL_W_PORT, RIGHT_HALL_W_PIN); + uint8_t hall_ur = !(RIGHT_HALL_U_PORT->IDR & RIGHT_HALL_U_PIN); + uint8_t hall_vr = !(RIGHT_HALL_V_PORT->IDR & RIGHT_HALL_V_PIN); + uint8_t hall_wr = !(RIGHT_HALL_W_PORT->IDR & RIGHT_HALL_W_PIN); uint8_t halll = hall_ul * 1 + hall_vl * 2 + hall_wl * 4; - posl = hall_to_pos[halll]; + posl = hall_to_pos[halll]; posl += 2; posl %= 6; uint8_t hallr = hall_ur * 1 + hall_vr * 2 + hall_wr * 4; - posr = hall_to_pos[hallr]; + posr = hall_to_pos[hallr]; posr += 2; posr %= 6; @@ -174,11 +172,10 @@ void DMA1_Channel1_IRQHandler(){ // timer = 0; // } // last_pos = pos; - + block(pwml, posl, &ul, &vl, &wl); block(pwmr, posr, &ur, &vr, &wr); - LEFT_TIM->LEFT_TIM_U = CLAMP(ul + pwm_res / 2, 0, pwm_res); LEFT_TIM->LEFT_TIM_V = CLAMP(vl + pwm_res / 2, 0, pwm_res); LEFT_TIM->LEFT_TIM_W = CLAMP(wl + pwm_res / 2, 0, pwm_res); @@ -186,13 +183,12 @@ void DMA1_Channel1_IRQHandler(){ RIGHT_TIM->RIGHT_TIM_U = CLAMP(ur + pwm_res / 2, 0, pwm_res); RIGHT_TIM->RIGHT_TIM_V = CLAMP(vr + pwm_res / 2, 0, pwm_res); RIGHT_TIM->RIGHT_TIM_W = CLAMP(wr + pwm_res / 2, 0, pwm_res); + HAL_GPIO_WritePin(LED_PORT, LED_PIN, 0); } int milli_vel_error_sum = 0; -int main(void) -{ - +int main(void) { HAL_Init(); __HAL_RCC_AFIO_CLK_ENABLE(); HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); @@ -222,12 +218,11 @@ int main(void) UART_Init(); HAL_GPIO_WritePin(OFF_PORT, OFF_PIN, 1); - + HAL_ADC_Start(&hadc1); HAL_ADC_Start(&hadc2); - while (1) - { + while(1) { HAL_Delay(0); // int milli_cur = 3000; // int milli_volt = milli_cur * MILLI_R / 1000;// + vel * MILLI_PSI * 141; @@ -252,43 +247,40 @@ int main(void) /** System Clock Configuration */ -void SystemClock_Config(void) -{ - +void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInit; - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = 16; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; HAL_RCC_OscConfig(&RCC_OscInitStruct); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2); PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; - PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8; + PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV8; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); - /**Configure the Systick interrupt time + /**Configure the Systick interrupt time */ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000); - /**Configure the Systick + /**Configure the Systick */ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); diff --git a/Src/setup.c b/Src/setup.c index c187106..e4528ab 100644 --- a/Src/setup.c +++ b/Src/setup.c @@ -18,6 +18,22 @@ * along with this program. If not, see . */ +/* +tim1 master, enable -> trgo +tim8, gated slave mode, trgo by tim1 trgo. overflow -> trgo +adc1,adc2 triggered by tim8 trgo +adc 1,2 dual mode + +ADC1 ADC2 +R_Blau PC4 CH14 R_Gelb PC5 CH15 +L_Grün PA0 CH01 L_Blau PC3 CH13 +R_DC PC1 CH11 L_DC PC0 CH10 +BAT PC2 CH12 L_TX PA2 CH02 +BAT PC2 CH12 L_RX PA3 CH03 + +pb10 usart3 dma1 channel2/3 +*/ + #include "defines.h" TIM_HandleTypeDef htim_right; @@ -26,42 +42,39 @@ ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc2; volatile adc_buf_t adc_buffer; -void UART_Init(){ +void UART_Init() { __HAL_RCC_USART3_CLK_ENABLE(); __HAL_RCC_DMA1_CLK_ENABLE(); UART_HandleTypeDef huart3; - huart3.Instance = USART3; - huart3.Init.BaudRate = 115200; - huart3.Init.WordLength = UART_WORDLENGTH_8B; - huart3.Init.StopBits = UART_STOPBITS_1; - huart3.Init.Parity = UART_PARITY_NONE; - huart3.Init.Mode = UART_MODE_TX; - huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; huart3.Init.OverSampling = UART_OVERSAMPLING_16; HAL_UART_Init(&huart3); - USART3->CR3 |= USART_CR3_DMAT;// | USART_CR3_DMAR | USART_CR3_OVRDIS; + USART3->CR3 |= USART_CR3_DMAT; // | USART_CR3_DMAR | USART_CR3_OVRDIS; GPIO_InitTypeDef GPIO_InitStruct; - GPIO_InitStruct.Pin = GPIO_PIN_10; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - DMA1_Channel2->CCR = 0; - DMA1_Channel2->CPAR = (uint32_t)&(USART3->DR); + DMA1_Channel2->CCR = 0; + DMA1_Channel2->CPAR = (uint32_t) & (USART3->DR); DMA1_Channel2->CNDTR = 0; - DMA1_Channel2->CCR = DMA_CCR_MINC | DMA_CCR_DIR; - DMA1->IFCR = DMA_IFCR_CTCIF2 | DMA_IFCR_CHTIF2 | DMA_IFCR_CGIF2; + DMA1_Channel2->CCR = DMA_CCR_MINC | DMA_CCR_DIR; + DMA1->IFCR = DMA_IFCR_CTCIF2 | DMA_IFCR_CHTIF2 | DMA_IFCR_CGIF2; } - -void MX_GPIO_Init(void) -{ - +void MX_GPIO_Init(void) { GPIO_InitTypeDef GPIO_InitStruct; /* GPIO Ports Clock Enable */ @@ -69,9 +82,9 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Pin = LEFT_HALL_U_PIN; HAL_GPIO_Init(LEFT_HALL_U_PORT, &GPIO_InitStruct); @@ -108,7 +121,7 @@ void MX_GPIO_Init(void) GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - + GPIO_InitStruct.Pin = LEFT_DC_CUR_PIN; HAL_GPIO_Init(LEFT_DC_CUR_PORT, &GPIO_InitStruct); @@ -131,7 +144,7 @@ void MX_GPIO_Init(void) HAL_GPIO_Init(DCLINK_PORT, &GPIO_InitStruct); GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - + GPIO_InitStruct.Pin = LEFT_TIM_UH_PIN; HAL_GPIO_Init(LEFT_TIM_UH_PORT, &GPIO_InitStruct); @@ -169,83 +182,83 @@ void MX_GPIO_Init(void) HAL_GPIO_Init(RIGHT_TIM_WL_PORT, &GPIO_InitStruct); } -void MX_TIM_Init(void){ +void MX_TIM_Init(void) { __HAL_RCC_TIM1_CLK_ENABLE(); __HAL_RCC_TIM8_CLK_ENABLE(); - + TIM_MasterConfigTypeDef sMasterConfig; TIM_OC_InitTypeDef sConfigOC; TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig; TIM_SlaveConfigTypeDef sTimConfig; - htim_right.Instance = RIGHT_TIM; - htim_right.Init.Prescaler = 0; - htim_right.Init.CounterMode = TIM_COUNTERMODE_CENTERALIGNED1; - htim_right.Init.Period = 64000000 / 2 / PWM_FREQ; - htim_right.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim_right.Instance = RIGHT_TIM; + htim_right.Init.Prescaler = 0; + htim_right.Init.CounterMode = TIM_COUNTERMODE_CENTERALIGNED1; + htim_right.Init.Period = 64000000 / 2 / PWM_FREQ; + htim_right.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim_right.Init.RepetitionCounter = 0; htim_right.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; HAL_TIM_PWM_Init(&htim_right); sMasterConfig.MasterOutputTrigger = TIM_TRGO_ENABLE; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; HAL_TIMEx_MasterConfigSynchronization(&htim_right, &sMasterConfig); - sConfigOC.OCMode = TIM_OCMODE_PWM1; - sConfigOC.Pulse = 0; - sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; - sConfigOC.OCNPolarity = TIM_OCNPOLARITY_LOW; - sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; - sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCNPolarity = TIM_OCNPOLARITY_LOW; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_SET; HAL_TIM_PWM_ConfigChannel(&htim_right, &sConfigOC, TIM_CHANNEL_1); HAL_TIM_PWM_ConfigChannel(&htim_right, &sConfigOC, TIM_CHANNEL_2); HAL_TIM_PWM_ConfigChannel(&htim_right, &sConfigOC, TIM_CHANNEL_3); - sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_ENABLE; + sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_ENABLE; sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_ENABLE; - sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; - sBreakDeadTimeConfig.DeadTime = DEAD_TIME; - sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; - sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_LOW; - sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; + sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; + sBreakDeadTimeConfig.DeadTime = DEAD_TIME; + sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; + sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_LOW; + sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; HAL_TIMEx_ConfigBreakDeadTime(&htim_right, &sBreakDeadTimeConfig); - htim_left.Instance = LEFT_TIM; - htim_left.Init.Prescaler = 0; - htim_left.Init.CounterMode = TIM_COUNTERMODE_CENTERALIGNED1; - htim_left.Init.Period = 64000000 / 2 / PWM_FREQ; - htim_left.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim_left.Instance = LEFT_TIM; + htim_left.Init.Prescaler = 0; + htim_left.Init.CounterMode = TIM_COUNTERMODE_CENTERALIGNED1; + htim_left.Init.Period = 64000000 / 2 / PWM_FREQ; + htim_left.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim_left.Init.RepetitionCounter = 0; htim_left.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; HAL_TIM_PWM_Init(&htim_left); sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; HAL_TIMEx_MasterConfigSynchronization(&htim_left, &sMasterConfig); sTimConfig.InputTrigger = TIM_TS_ITR0; - sTimConfig.SlaveMode = TIM_SLAVEMODE_GATED; + sTimConfig.SlaveMode = TIM_SLAVEMODE_GATED; HAL_TIM_SlaveConfigSynchronization(&htim_left, &sTimConfig); - sConfigOC.OCMode = TIM_OCMODE_PWM1; - sConfigOC.Pulse = 0; - sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; - sConfigOC.OCNPolarity = TIM_OCNPOLARITY_LOW; - sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; - sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCNPolarity = TIM_OCNPOLARITY_LOW; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_SET; HAL_TIM_PWM_ConfigChannel(&htim_left, &sConfigOC, TIM_CHANNEL_1); HAL_TIM_PWM_ConfigChannel(&htim_left, &sConfigOC, TIM_CHANNEL_2); HAL_TIM_PWM_ConfigChannel(&htim_left, &sConfigOC, TIM_CHANNEL_3); - sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_ENABLE; + sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_ENABLE; sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_ENABLE; - sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; - sBreakDeadTimeConfig.DeadTime = DEAD_TIME; - sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; - sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_LOW; - sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; + sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; + sBreakDeadTimeConfig.DeadTime = DEAD_TIME; + sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; + sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_LOW; + sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; HAL_TIMEx_ConfigBreakDeadTime(&htim_left, &sBreakDeadTimeConfig); HAL_TIM_PWM_Start(&htim_left, TIM_CHANNEL_1); @@ -267,27 +280,26 @@ void MX_TIM_Init(void){ __HAL_TIM_ENABLE(&htim_right); } -void MX_ADC1_Init(void) -{ +void MX_ADC1_Init(void) { ADC_MultiModeTypeDef multimode; ADC_ChannelConfTypeDef sConfig; __HAL_RCC_ADC1_CLK_ENABLE(); - hadc1.Instance = ADC1; - hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; - hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Instance = ADC1; + hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; + hadc1.Init.ContinuousConvMode = DISABLE; hadc1.Init.DiscontinuousConvMode = DISABLE; - hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T8_TRGO; - hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc1.Init.NbrOfConversion = 5; + hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T8_TRGO; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.NbrOfConversion = 5; HAL_ADC_Init(&hadc1); - /**Enable or disable the remapping of ADC1_ETRGREG: + /**Enable or disable the remapping of ADC1_ETRGREG: * ADC1 External Event regular conversion is connected to TIM8 TRG0 */ __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE(); - /**Configure the ADC multi-mode + /**Configure the ADC multi-mode */ multimode.Mode = ADC_DUALMODE_REGSIMULT; HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode); @@ -295,23 +307,23 @@ void MX_ADC1_Init(void) sConfig.SamplingTime = ADC_SAMPLETIME_13CYCLES_5; sConfig.Channel = ADC_CHANNEL_14; - sConfig.Rank = 1; + sConfig.Rank = 1; HAL_ADC_ConfigChannel(&hadc1, &sConfig); sConfig.Channel = ADC_CHANNEL_1; - sConfig.Rank = 2; + sConfig.Rank = 2; HAL_ADC_ConfigChannel(&hadc1, &sConfig); sConfig.Channel = ADC_CHANNEL_11; - sConfig.Rank = 3; + sConfig.Rank = 3; HAL_ADC_ConfigChannel(&hadc1, &sConfig); sConfig.Channel = ADC_CHANNEL_12; - sConfig.Rank = 4; + sConfig.Rank = 4; HAL_ADC_ConfigChannel(&hadc1, &sConfig); sConfig.Channel = ADC_CHANNEL_12; - sConfig.Rank = 5; + sConfig.Rank = 5; HAL_ADC_ConfigChannel(&hadc1, &sConfig); hadc1.Instance->CR2 |= ADC_CR2_DMA; @@ -320,11 +332,11 @@ void MX_ADC1_Init(void) __HAL_RCC_DMA1_CLK_ENABLE(); - DMA1_Channel1->CCR = 0; + DMA1_Channel1->CCR = 0; DMA1_Channel1->CNDTR = 5; - DMA1_Channel1->CPAR = (uint32_t)&(ADC1->DR); - DMA1_Channel1->CMAR = (uint32_t)&adc_buffer; - DMA1_Channel1->CCR = DMA_CCR_MSIZE_1 | DMA_CCR_PSIZE_1 | DMA_CCR_MINC | DMA_CCR_CIRC | DMA_CCR_TCIE; + DMA1_Channel1->CPAR = (uint32_t) & (ADC1->DR); + DMA1_Channel1->CMAR = (uint32_t)&adc_buffer; + DMA1_Channel1->CCR = DMA_CCR_MSIZE_1 | DMA_CCR_PSIZE_1 | DMA_CCR_MINC | DMA_CCR_CIRC | DMA_CCR_TCIE; DMA1_Channel1->CCR |= DMA_CCR_EN; HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); @@ -332,45 +344,44 @@ void MX_ADC1_Init(void) } /* ADC2 init function */ -void MX_ADC2_Init(void) -{ +void MX_ADC2_Init(void) { ADC_ChannelConfTypeDef sConfig; __HAL_RCC_ADC2_CLK_ENABLE(); // HAL_ADC_DeInit(&hadc2); // hadc2.Instance->CR2 = 0; - /**Common config + /**Common config */ - hadc2.Instance = ADC2; - hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; - hadc2.Init.ContinuousConvMode = DISABLE; + hadc2.Instance = ADC2; + hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; + hadc2.Init.ContinuousConvMode = DISABLE; hadc2.Init.DiscontinuousConvMode = DISABLE; - hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; - hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc2.Init.NbrOfConversion = 5; + hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc2.Init.NbrOfConversion = 5; HAL_ADC_Init(&hadc2); sConfig.SamplingTime = ADC_SAMPLETIME_13CYCLES_5; sConfig.Channel = ADC_CHANNEL_15; - sConfig.Rank = 1; + sConfig.Rank = 1; HAL_ADC_ConfigChannel(&hadc2, &sConfig); sConfig.Channel = ADC_CHANNEL_13; - sConfig.Rank = 2; + sConfig.Rank = 2; HAL_ADC_ConfigChannel(&hadc2, &sConfig); sConfig.Channel = ADC_CHANNEL_10; - sConfig.Rank = 3; + sConfig.Rank = 3; HAL_ADC_ConfigChannel(&hadc2, &sConfig); sConfig.Channel = ADC_CHANNEL_2; - sConfig.Rank = 4; + sConfig.Rank = 4; HAL_ADC_ConfigChannel(&hadc2, &sConfig); sConfig.Channel = ADC_CHANNEL_3; - sConfig.Rank = 5; + sConfig.Rank = 5; HAL_ADC_ConfigChannel(&hadc2, &sConfig); hadc2.Instance->CR2 |= ADC_CR2_DMA; diff --git a/Src/stm32f1xx_it.c b/Src/stm32f1xx_it.c index 4ce2b1c..b5d8a68 100644 --- a/Src/stm32f1xx_it.c +++ b/Src/stm32f1xx_it.c @@ -43,14 +43,13 @@ /******************************************************************************/ -/* Cortex-M3 Processor Interruption and Exception Handlers */ +/* Cortex-M3 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ -void NMI_Handler(void) -{ +void NMI_Handler(void) { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ @@ -62,13 +61,11 @@ void NMI_Handler(void) /** * @brief This function handles Hard fault interrupt. */ -void HardFault_Handler(void) -{ +void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ - while (1) - { + while(1) { } /* USER CODE BEGIN HardFault_IRQn 1 */ @@ -78,13 +75,11 @@ void HardFault_Handler(void) /** * @brief This function handles Memory management fault. */ -void MemManage_Handler(void) -{ +void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { + while(1) { } /* USER CODE BEGIN MemoryManagement_IRQn 1 */ @@ -94,13 +89,11 @@ void MemManage_Handler(void) /** * @brief This function handles Prefetch fault, memory access fault. */ -void BusFault_Handler(void) -{ +void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ - while (1) - { + while(1) { } /* USER CODE BEGIN BusFault_IRQn 1 */ @@ -110,13 +103,11 @@ void BusFault_Handler(void) /** * @brief This function handles Undefined instruction or illegal state. */ -void UsageFault_Handler(void) -{ +void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { + while(1) { } /* USER CODE BEGIN UsageFault_IRQn 1 */ @@ -126,8 +117,7 @@ void UsageFault_Handler(void) /** * @brief This function handles System service call via SWI instruction. */ -void SVC_Handler(void) -{ +void SVC_Handler(void) { /* USER CODE BEGIN SVCall_IRQn 0 */ /* USER CODE END SVCall_IRQn 0 */ @@ -139,8 +129,7 @@ void SVC_Handler(void) /** * @brief This function handles Debug monitor. */ -void DebugMon_Handler(void) -{ +void DebugMon_Handler(void) { /* USER CODE BEGIN DebugMonitor_IRQn 0 */ /* USER CODE END DebugMonitor_IRQn 0 */ @@ -152,8 +141,7 @@ void DebugMon_Handler(void) /** * @brief This function handles Pendable request for system service. */ -void PendSV_Handler(void) -{ +void PendSV_Handler(void) { /* USER CODE BEGIN PendSV_IRQn 0 */ /* USER CODE END PendSV_IRQn 0 */ @@ -165,8 +153,7 @@ void PendSV_Handler(void) /** * @brief This function handles System tick timer. */ -void SysTick_Handler(void) -{ +void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ @@ -185,7 +172,6 @@ void SysTick_Handler(void) /******************************************************************************/ - /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Src/system_stm32f1xx.c b/Src/system_stm32f1xx.c index af3759a..bb1a3ab 100644 --- a/Src/system_stm32f1xx.c +++ b/Src/system_stm32f1xx.c @@ -68,8 +68,8 @@ /** @addtogroup stm32f1xx_system * @{ - */ - + */ + /** @addtogroup STM32F1xx_System_Private_Includes * @{ */ @@ -92,26 +92,26 @@ * @{ */ -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz. - This value can be provided and adapted by the user application. */ +#if !defined(HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz. \ + This value can be provided and adapted by the user application. */ #endif /* HSE_VALUE */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ +#if !defined(HSI_VALUE) +#define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. \ + This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ -/*!< Uncomment the following line if you need to use external SRAM */ +/*!< Uncomment the following line if you need to use external SRAM */ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) /* #define DATA_IN_ExtSRAM */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ /*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ + Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. \ + This value must be a multiple of 0x200. */ /** @@ -133,14 +133,14 @@ /******************************************************************************* * Clock Definitions *******************************************************************************/ -#if defined(STM32F100xB) ||defined(STM32F100xE) - uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */ +#if defined(STM32F100xB) || defined(STM32F100xE) +uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */ #else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = 72000000U; /*!< System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock = 72000000U; /*!< System Clock Frequency (Core Clock) */ #endif const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; +const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} @@ -152,7 +152,7 @@ const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); +static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ @@ -172,19 +172,18 @@ const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; * @param None * @retval None */ -void SystemInit (void) -{ +void SystemInit(void) { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= 0x00000001U; - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #if !defined(STM32F105xC) && !defined(STM32F107xC) RCC->CFGR &= 0xF8FF0000U; #else RCC->CFGR &= 0xF0FF0000U; -#endif /* STM32F105xC */ - +#endif /* STM32F105xC */ + /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= 0xFEF6FFFFU; @@ -208,23 +207,23 @@ void SystemInit (void) RCC->CIR = 0x009F0000U; /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000U; + RCC->CFGR2 = 0x00000000U; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000U; #endif /* STM32F105xC */ - + #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) - #ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); - #endif /* DATA_IN_ExtSRAM */ -#endif +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ +#endif #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif } /** @@ -262,8 +261,7 @@ void SystemInit (void) * @param None * @retval None */ -void SystemCoreClockUpdate (void) -{ +void SystemCoreClockUpdate(void) { uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; #if defined(STM32F105xC) || defined(STM32F107xC) @@ -273,101 +271,85 @@ void SystemCoreClockUpdate (void) #if defined(STM32F100xB) || defined(STM32F100xE) uint32_t prediv1factor = 0U; #endif /* STM32F100xB or STM32F100xE */ - + /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00U: /* HSI used as system clock */ + + switch(tmp) { + case 0x00U: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; - case 0x04U: /* HSE used as system clock */ + case 0x04U: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; - case 0x08U: /* PLL used as system clock */ + case 0x08U: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - -#if !defined(STM32F105xC) && !defined(STM32F107xC) - pllmull = ( pllmull >> 18U) + 2U; - - if (pllsource == 0x00U) - { + +#if !defined(STM32F105xC) && !defined(STM32F107xC) + pllmull = (pllmull >> 18U) + 2U; + + if(pllsource == 0x00U) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; - } - else - { - #if defined(STM32F100xB) || defined(STM32F100xE) - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - #else + } else { +#if defined(STM32F100xB) || defined(STM32F100xE) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; +#else /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ + if((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) { /* HSE oscillator clock divided by 2 */ SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; - } - else - { + } else { SystemCoreClock = HSE_VALUE * pllmull; } - #endif +#endif } #else pllmull = pllmull >> 18U; - - if (pllmull != 0x0DU) - { - pllmull += 2U; + + if(pllmull != 0x0DU) { + pllmull += 2U; + } else { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13U / 2U; } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13U / 2U; - } - - if (pllsource == 0x00U) - { + + if(pllsource == 0x00U) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - + } else { /* PREDIV1 selected as PLL clock entry */ + /* Get PREDIV1 clock source and division factor */ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; - - if (prediv1source == 0U) - { + + if(prediv1source == 0U) { /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } else { /* PLL2 clock selected as PREDIV1 clock entry */ + /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; - pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; - SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } -#endif /* STM32F105xC */ +#endif /* STM32F105xC */ break; default: SystemCoreClock = HSI_VALUE; break; } - + /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ - SystemCoreClock >>= tmp; + SystemCoreClock >>= tmp; } #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) @@ -376,7 +358,7 @@ void SystemCoreClockUpdate (void) * before jump to __main * @param None * @retval None - */ + */ #ifdef DATA_IN_ExtSRAM /** * @brief Setup the external memory controller. @@ -386,9 +368,8 @@ void SystemCoreClockUpdate (void) * data memory (including heap and stack). * @param None * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ + */ +void SystemInit_ExtMemCtl(void) { __IO uint32_t tmpreg; /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is required, then adjust the Register Addresses */ @@ -398,36 +379,36 @@ void SystemInit_ExtMemCtl(void) /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); - + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ RCC->APB2ENR = 0x000001E0U; - + /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); (void)(tmpreg); - -/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ -/*---------------- SRAM Address lines configuration -------------------------*/ -/*---------------- NOE and NWE configuration --------------------------------*/ -/*---------------- NE3 configuration ----------------------------------------*/ -/*---------------- NBL0, NBL1 configuration ---------------------------------*/ - - GPIOD->CRL = 0x44BB44BBU; + + /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ + /*---------------- SRAM Address lines configuration -------------------------*/ + /*---------------- NOE and NWE configuration --------------------------------*/ + /*---------------- NE3 configuration ----------------------------------------*/ + /*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BBU; GPIOD->CRH = 0xBBBBBBBBU; - GPIOE->CRL = 0xB44444BBU; + GPIOE->CRL = 0xB44444BBU; GPIOE->CRH = 0xBBBBBBBBU; - GPIOF->CRL = 0x44BBBBBBU; + GPIOF->CRL = 0x44BBBBBBU; GPIOF->CRH = 0xBBBB4444U; - GPIOG->CRL = 0x44BBBBBBU; + GPIOG->CRL = 0x44BBBBBBU; GPIOG->CRH = 0x444B4B44U; - -/*---------------- FSMC Configuration ---------------------------------------*/ -/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ - + + /*---------------- FSMC Configuration ---------------------------------------*/ + /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + FSMC_Bank1->BTCR[4U] = 0x00001091U; FSMC_Bank1->BTCR[5U] = 0x00110212U; } @@ -441,8 +422,8 @@ void SystemInit_ExtMemCtl(void) /** * @} */ - + /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/