/* * File: BLDC_controller.c * * Code generated for Simulink model 'BLDC_controller'. * * Model version : 1.1296 * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 * C/C++ source code generated on : Tue Oct 20 17:29:57 2020 * * Target selection: ert.tlc * Embedded hardware selection: ARM Compatible->ARM Cortex * Emulation hardware selection: * Differs from embedded hardware (MATLAB Host) * Code generation objectives: * 1. Execution efficiency * 2. RAM efficiency * Validation result: Not run */ #include "BLDC_controller.h" /* Named constants for Chart: '/F03_02_Control_Mode_Manager' */ #define IN_ACTIVE ((uint8_T)1U) #define IN_NO_ACTIVE_CHILD ((uint8_T)0U) #define IN_OPEN ((uint8_T)2U) #define IN_SPEED_MODE ((uint8_T)1U) #define IN_TORQUE_MODE ((uint8_T)2U) #define IN_VOLTAGE_MODE ((uint8_T)3U) #define OPEN_MODE ((uint8_T)0U) #define SPD_MODE ((uint8_T)2U) #define TRQ_MODE ((uint8_T)3U) #define VLT_MODE ((uint8_T)1U) #ifndef UCHAR_MAX #include #endif #if ( UCHAR_MAX != (0xFFU) ) || ( SCHAR_MAX != (0x7F) ) #error Code was generated for compiler with different sized uchar/char. \ Consider adjusting Test hardware word size settings on the \ Hardware Implementation pane to match your compiler word sizes as \ defined in limits.h of the compiler. Alternatively, you can \ select the Test hardware is the same as production hardware option and \ select the Enable portable word sizes option on the Code Generation > \ Verification pane for ERT based targets, which will disable the \ preprocessor word size checks. #endif #if ( USHRT_MAX != (0xFFFFU) ) || ( SHRT_MAX != (0x7FFF) ) #error Code was generated for compiler with different sized ushort/short. \ Consider adjusting Test hardware word size settings on the \ Hardware Implementation pane to match your compiler word sizes as \ defined in limits.h of the compiler. Alternatively, you can \ select the Test hardware is the same as production hardware option and \ select the Enable portable word sizes option on the Code Generation > \ Verification pane for ERT based targets, which will disable the \ preprocessor word size checks. #endif #if ( UINT_MAX != (0xFFFFFFFFU) ) || ( INT_MAX != (0x7FFFFFFF) ) #error Code was generated for compiler with different sized uint/int. \ Consider adjusting Test hardware word size settings on the \ Hardware Implementation pane to match your compiler word sizes as \ defined in limits.h of the compiler. Alternatively, you can \ select the Test hardware is the same as production hardware option and \ select the Enable portable word sizes option on the Code Generation > \ Verification pane for ERT based targets, which will disable the \ preprocessor word size checks. #endif #if ( ULONG_MAX != (0xFFFFFFFFU) ) || ( LONG_MAX != (0x7FFFFFFF) ) #error Code was generated for compiler with different sized ulong/long. \ Consider adjusting Test hardware word size settings on the \ Hardware Implementation pane to match your compiler word sizes as \ defined in limits.h of the compiler. Alternatively, you can \ select the Test hardware is the same as production hardware option and \ select the Enable portable word sizes option on the Code Generation > \ Verification pane for ERT based targets, which will disable the \ preprocessor word size checks. #endif #if 0 /* Skip this size verification because of preprocessor limitation */ #if ( ULLONG_MAX != (0xFFFFFFFFFFFFFFFFULL) ) || ( LLONG_MAX != (0x7FFFFFFFFFFFFFFFLL) ) #error Code was generated for compiler with different sized ulong_long/long_long. \ Consider adjusting Test hardware word size settings on the \ Hardware Implementation pane to match your compiler word sizes as \ defined in limits.h of the compiler. Alternatively, you can \ select the Test hardware is the same as production hardware option and \ select the Enable portable word sizes option on the Code Generation > \ Verification pane for ERT based targets, which will disable the \ preprocessor word size checks. #endif #endif uint8_T plook_u8s16_evencka(int16_T u, int16_T bp0, uint16_T bpSpace, uint32_T maxIndex); uint8_T plook_u8u16_evencka(uint16_T u, uint16_T bp0, uint16_T bpSpace, uint32_T maxIndex); int32_T div_nde_s32_floor(int32_T numerator, int32_T denominator); extern void Counter_Init(DW_Counter *localDW, int16_T rtp_z_cntInit); extern int16_T Counter(int16_T rtu_inc, int16_T rtu_max, boolean_T rtu_rst, DW_Counter *localDW); extern void Low_Pass_Filter_Reset(DW_Low_Pass_Filter *localDW); extern void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T rty_y[2], DW_Low_Pass_Filter *localDW); extern void Counter_b_Init(DW_Counter_b *localDW, uint16_T rtp_z_cntInit); extern void Counter_n(uint16_T rtu_inc, uint16_T rtu_max, boolean_T rtu_rst, uint16_T *rty_cnt, DW_Counter_b *localDW); extern void either_edge(boolean_T rtu_u, boolean_T *rty_y, DW_either_edge *localDW); extern void Debounce_Filter_Init(DW_Debounce_Filter *localDW); extern void Debounce_Filter(boolean_T rtu_u, uint16_T rtu_tAcv, uint16_T rtu_tDeacv, boolean_T *rty_y, DW_Debounce_Filter *localDW); extern void I_backCalc_fixdt_Init(DW_I_backCalc_fixdt *localDW, int32_T rtp_yInit); extern void I_backCalc_fixdt_Reset(DW_I_backCalc_fixdt *localDW, int32_T rtp_yInit); extern void I_backCalc_fixdt(int16_T rtu_err, uint16_T rtu_I, uint16_T rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T *rty_out, DW_I_backCalc_fixdt * localDW); extern void PI_clamp_fixdt_Init(DW_PI_clamp_fixdt *localDW); extern void PI_clamp_fixdt_Reset(DW_PI_clamp_fixdt *localDW); extern void PI_clamp_fixdt(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, int32_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt *localDW); extern void PI_clamp_fixdt_d_Init(DW_PI_clamp_fixdt_m *localDW); extern void PI_clamp_fixdt_b_Reset(DW_PI_clamp_fixdt_m *localDW); extern void PI_clamp_fixdt_l(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, int16_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt_m *localDW); extern void PI_clamp_fixdt_f_Init(DW_PI_clamp_fixdt_g *localDW); extern void PI_clamp_fixdt_g_Reset(DW_PI_clamp_fixdt_g *localDW); extern void PI_clamp_fixdt_k(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, int16_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt_g *localDW); uint8_T plook_u8s16_evencka(int16_T u, int16_T bp0, uint16_T bpSpace, uint32_T maxIndex) { uint8_T bpIndex; uint16_T fbpIndex; /* Prelookup - Index only Index Search method: 'even' Extrapolation method: 'Clip' Use previous index: 'off' Use last breakpoint for index at or above upper limit: 'on' Remove protection against out-of-range input in generated code: 'off' */ if (u <= bp0) { bpIndex = 0U; } else { fbpIndex = (uint16_T)((uint32_T)(uint16_T)(u - bp0) / bpSpace); if (fbpIndex < maxIndex) { bpIndex = (uint8_T)fbpIndex; } else { bpIndex = (uint8_T)maxIndex; } } return bpIndex; } uint8_T plook_u8u16_evencka(uint16_T u, uint16_T bp0, uint16_T bpSpace, uint32_T maxIndex) { uint8_T bpIndex; uint16_T fbpIndex; /* Prelookup - Index only Index Search method: 'even' Extrapolation method: 'Clip' Use previous index: 'off' Use last breakpoint for index at or above upper limit: 'on' Remove protection against out-of-range input in generated code: 'off' */ if (u <= bp0) { bpIndex = 0U; } else { fbpIndex = (uint16_T)((uint32_T)(uint16_T)((uint32_T)u - bp0) / bpSpace); if (fbpIndex < maxIndex) { bpIndex = (uint8_T)fbpIndex; } else { bpIndex = (uint8_T)maxIndex; } } return bpIndex; } int32_T div_nde_s32_floor(int32_T numerator, int32_T denominator) { return (((numerator < 0) != (denominator < 0)) && (numerator % denominator != 0) ? -1 : 0) + numerator / denominator; } /* System initialize for atomic system: '/Counter' */ void Counter_Init(DW_Counter *localDW, int16_T rtp_z_cntInit) { /* InitializeConditions for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = rtp_z_cntInit; } /* Output and update for atomic system: '/Counter' */ int16_T Counter(int16_T rtu_inc, int16_T rtu_max, boolean_T rtu_rst, DW_Counter * localDW) { int16_T rtu_rst_0; int16_T rty_cnt_0; /* Switch: '/Switch1' incorporates: * Constant: '/Constant23' * UnitDelay: '/UnitDelay' */ if (rtu_rst) { rtu_rst_0 = 0; } else { rtu_rst_0 = localDW->UnitDelay_DSTATE; } /* End of Switch: '/Switch1' */ /* Sum: '/Sum1' */ rty_cnt_0 = (int16_T)(rtu_inc + rtu_rst_0); /* MinMax: '/MinMax' */ if (rty_cnt_0 < rtu_max) { /* Update for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = rty_cnt_0; } else { /* Update for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = rtu_max; } /* End of MinMax: '/MinMax' */ return rty_cnt_0; } /* System reset for atomic system: '/Low_Pass_Filter' */ void Low_Pass_Filter_Reset(DW_Low_Pass_Filter *localDW) { /* InitializeConditions for UnitDelay: '/UnitDelay1' */ localDW->UnitDelay1_DSTATE[0] = 0; localDW->UnitDelay1_DSTATE[1] = 0; } /* Output and update for atomic system: '/Low_Pass_Filter' */ void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T rty_y[2], DW_Low_Pass_Filter *localDW) { int32_T rtb_Sum3_g; /* Sum: '/Sum2' incorporates: * UnitDelay: '/UnitDelay1' */ rtb_Sum3_g = rtu_u[0] - (localDW->UnitDelay1_DSTATE[0] >> 16); if (rtb_Sum3_g > 32767) { rtb_Sum3_g = 32767; } else { if (rtb_Sum3_g < -32768) { rtb_Sum3_g = -32768; } } /* Sum: '/Sum3' incorporates: * Product: '/Divide3' * Sum: '/Sum2' * UnitDelay: '/UnitDelay1' */ rtb_Sum3_g = rtu_coef * rtb_Sum3_g + localDW->UnitDelay1_DSTATE[0]; /* DataTypeConversion: '/Data Type Conversion' */ rty_y[0] = (int16_T)(rtb_Sum3_g >> 16); /* Update for UnitDelay: '/UnitDelay1' */ localDW->UnitDelay1_DSTATE[0] = rtb_Sum3_g; /* Sum: '/Sum2' incorporates: * UnitDelay: '/UnitDelay1' */ rtb_Sum3_g = rtu_u[1] - (localDW->UnitDelay1_DSTATE[1] >> 16); if (rtb_Sum3_g > 32767) { rtb_Sum3_g = 32767; } else { if (rtb_Sum3_g < -32768) { rtb_Sum3_g = -32768; } } /* Sum: '/Sum3' incorporates: * Product: '/Divide3' * Sum: '/Sum2' * UnitDelay: '/UnitDelay1' */ rtb_Sum3_g = rtu_coef * rtb_Sum3_g + localDW->UnitDelay1_DSTATE[1]; /* DataTypeConversion: '/Data Type Conversion' */ rty_y[1] = (int16_T)(rtb_Sum3_g >> 16); /* Update for UnitDelay: '/UnitDelay1' */ localDW->UnitDelay1_DSTATE[1] = rtb_Sum3_g; } /* * System initialize for atomic system: * '/Counter' * '/Counter' */ void Counter_b_Init(DW_Counter_b *localDW, uint16_T rtp_z_cntInit) { /* InitializeConditions for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = rtp_z_cntInit; } /* * Output and update for atomic system: * '/Counter' * '/Counter' */ void Counter_n(uint16_T rtu_inc, uint16_T rtu_max, boolean_T rtu_rst, uint16_T *rty_cnt, DW_Counter_b *localDW) { uint16_T rtu_rst_0; /* Switch: '/Switch1' incorporates: * Constant: '/Constant23' * UnitDelay: '/UnitDelay' */ if (rtu_rst) { rtu_rst_0 = 0U; } else { rtu_rst_0 = localDW->UnitDelay_DSTATE; } /* End of Switch: '/Switch1' */ /* Sum: '/Sum1' */ *rty_cnt = (uint16_T)((uint32_T)rtu_inc + rtu_rst_0); /* MinMax: '/MinMax' */ if (*rty_cnt < rtu_max) { /* Update for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = *rty_cnt; } else { /* Update for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = rtu_max; } /* End of MinMax: '/MinMax' */ } /* * Output and update for atomic system: * '/either_edge' * '/either_edge' */ void either_edge(boolean_T rtu_u, boolean_T *rty_y, DW_either_edge *localDW) { /* RelationalOperator: '/Relational Operator' incorporates: * UnitDelay: '/UnitDelay' */ *rty_y = (rtu_u != localDW->UnitDelay_DSTATE); /* Update for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = rtu_u; } /* System initialize for atomic system: '/Debounce_Filter' */ void Debounce_Filter_Init(DW_Debounce_Filter *localDW) { /* SystemInitialize for IfAction SubSystem: '/Qualification' */ /* SystemInitialize for Atomic SubSystem: '/Counter' */ Counter_b_Init(&localDW->Counter_n1, 0U); /* End of SystemInitialize for SubSystem: '/Counter' */ /* End of SystemInitialize for SubSystem: '/Qualification' */ /* SystemInitialize for IfAction SubSystem: '/Dequalification' */ /* SystemInitialize for Atomic SubSystem: '/Counter' */ Counter_b_Init(&localDW->Counter_e, 0U); /* End of SystemInitialize for SubSystem: '/Counter' */ /* End of SystemInitialize for SubSystem: '/Dequalification' */ } /* Output and update for atomic system: '/Debounce_Filter' */ void Debounce_Filter(boolean_T rtu_u, uint16_T rtu_tAcv, uint16_T rtu_tDeacv, boolean_T *rty_y, DW_Debounce_Filter *localDW) { uint16_T rtb_Sum1_n; boolean_T rtb_RelationalOperator_g; /* Outputs for Atomic SubSystem: '/either_edge' */ either_edge(rtu_u, &rtb_RelationalOperator_g, &localDW->either_edge_p); /* End of Outputs for SubSystem: '/either_edge' */ /* If: '/If2' incorporates: * Constant: '/Constant6' * Constant: '/Constant6' * Inport: '/yPrev' * Logic: '/Logical Operator1' * Logic: '/Logical Operator2' * Logic: '/Logical Operator3' * Logic: '/Logical Operator4' * UnitDelay: '/UnitDelay' */ if (rtu_u && (!localDW->UnitDelay_DSTATE)) { /* Outputs for IfAction SubSystem: '/Qualification' incorporates: * ActionPort: '/Action Port' */ /* Outputs for Atomic SubSystem: '/Counter' */ Counter_n(1U, rtu_tAcv, rtb_RelationalOperator_g, &rtb_Sum1_n, &localDW->Counter_n1); /* End of Outputs for SubSystem: '/Counter' */ /* Switch: '/Switch2' incorporates: * Constant: '/Constant6' * RelationalOperator: '/Relational Operator2' */ *rty_y = ((rtb_Sum1_n > rtu_tAcv) || localDW->UnitDelay_DSTATE); /* End of Outputs for SubSystem: '/Qualification' */ } else if ((!rtu_u) && localDW->UnitDelay_DSTATE) { /* Outputs for IfAction SubSystem: '/Dequalification' incorporates: * ActionPort: '/Action Port' */ /* Outputs for Atomic SubSystem: '/Counter' */ Counter_n(1U, rtu_tDeacv, rtb_RelationalOperator_g, &rtb_Sum1_n, &localDW->Counter_e); /* End of Outputs for SubSystem: '/Counter' */ /* Switch: '/Switch2' incorporates: * Constant: '/Constant6' * RelationalOperator: '/Relational Operator2' */ *rty_y = ((!(rtb_Sum1_n > rtu_tDeacv)) && localDW->UnitDelay_DSTATE); /* End of Outputs for SubSystem: '/Dequalification' */ } else { /* Outputs for IfAction SubSystem: '/Default' incorporates: * ActionPort: '/Action Port' */ *rty_y = localDW->UnitDelay_DSTATE; /* End of Outputs for SubSystem: '/Default' */ } /* End of If: '/If2' */ /* Update for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = *rty_y; } /* * System initialize for atomic system: * '/I_backCalc_fixdt' * '/I_backCalc_fixdt1' * '/I_backCalc_fixdt' */ void I_backCalc_fixdt_Init(DW_I_backCalc_fixdt *localDW, int32_T rtp_yInit) { /* InitializeConditions for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE_m = rtp_yInit; } /* * System reset for atomic system: * '/I_backCalc_fixdt' * '/I_backCalc_fixdt1' * '/I_backCalc_fixdt' */ void I_backCalc_fixdt_Reset(DW_I_backCalc_fixdt *localDW, int32_T rtp_yInit) { /* InitializeConditions for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = 0; /* InitializeConditions for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE_m = rtp_yInit; } /* * Output and update for atomic system: * '/I_backCalc_fixdt' * '/I_backCalc_fixdt1' * '/I_backCalc_fixdt' */ void I_backCalc_fixdt(int16_T rtu_err, uint16_T rtu_I, uint16_T rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T *rty_out, DW_I_backCalc_fixdt *localDW) { int32_T rtb_Sum1_o; int16_T rtb_DataTypeConversion1_gf; /* Sum: '/Sum2' incorporates: * Product: '/Divide2' * UnitDelay: '/UnitDelay' */ rtb_Sum1_o = (rtu_err * rtu_I) >> 4; if ((rtb_Sum1_o < 0) && (localDW->UnitDelay_DSTATE < MIN_int32_T - rtb_Sum1_o)) { rtb_Sum1_o = MIN_int32_T; } else if ((rtb_Sum1_o > 0) && (localDW->UnitDelay_DSTATE > MAX_int32_T - rtb_Sum1_o)) { rtb_Sum1_o = MAX_int32_T; } else { rtb_Sum1_o += localDW->UnitDelay_DSTATE; } /* End of Sum: '/Sum2' */ /* Sum: '/Sum1' incorporates: * UnitDelay: '/UnitDelay' */ rtb_Sum1_o += localDW->UnitDelay_DSTATE_m; /* DataTypeConversion: '/Data Type Conversion1' */ rtb_DataTypeConversion1_gf = (int16_T)(rtb_Sum1_o >> 12); /* Switch: '/Switch2' incorporates: * RelationalOperator: '/LowerRelop1' * RelationalOperator: '/UpperRelop' * Switch: '/Switch' */ if (rtb_DataTypeConversion1_gf > rtu_satMax) { *rty_out = rtu_satMax; } else if (rtb_DataTypeConversion1_gf < rtu_satMin) { /* Switch: '/Switch' */ *rty_out = rtu_satMin; } else { *rty_out = rtb_DataTypeConversion1_gf; } /* End of Switch: '/Switch2' */ /* Update for UnitDelay: '/UnitDelay' incorporates: * Product: '/Divide1' * Sum: '/Sum3' */ localDW->UnitDelay_DSTATE = (int16_T)(*rty_out - rtb_DataTypeConversion1_gf) * rtu_Kb; /* Update for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE_m = rtb_Sum1_o; } /* System initialize for atomic system: '/PI_clamp_fixdt' */ void PI_clamp_fixdt_Init(DW_PI_clamp_fixdt *localDW) { /* InitializeConditions for Delay: '/Resettable Delay' */ localDW->icLoad = 1U; } /* System reset for atomic system: '/PI_clamp_fixdt' */ void PI_clamp_fixdt_Reset(DW_PI_clamp_fixdt *localDW) { /* InitializeConditions for UnitDelay: '/UnitDelay1' */ localDW->UnitDelay1_DSTATE = false; /* InitializeConditions for Delay: '/Resettable Delay' */ localDW->icLoad = 1U; } /* Output and update for atomic system: '/PI_clamp_fixdt' */ void PI_clamp_fixdt(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, int32_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt *localDW) { boolean_T rtb_LowerRelop1_c0; boolean_T rtb_UpperRelop_f; int32_T rtb_Sum1_p0; int32_T q0; int32_T tmp; int16_T tmp_0; /* Sum: '/Sum2' incorporates: * Product: '/Divide2' */ q0 = rtu_err * rtu_I; if ((q0 < 0) && (rtu_ext_limProt < MIN_int32_T - q0)) { q0 = MIN_int32_T; } else if ((q0 > 0) && (rtu_ext_limProt > MAX_int32_T - q0)) { q0 = MAX_int32_T; } else { q0 += rtu_ext_limProt; } /* Delay: '/Resettable Delay' */ if (localDW->icLoad != 0) { localDW->ResettableDelay_DSTATE = rtu_init; } /* Switch: '/Switch1' incorporates: * Constant: '/Constant' * Sum: '/Sum2' * UnitDelay: '/UnitDelay1' */ if (localDW->UnitDelay1_DSTATE) { tmp = 0; } else { tmp = q0; } /* End of Switch: '/Switch1' */ /* Sum: '/Sum1' incorporates: * Delay: '/Resettable Delay' */ rtb_Sum1_p0 = tmp + localDW->ResettableDelay_DSTATE; /* Product: '/Divide5' */ tmp = (rtu_err * rtu_P) >> 11; if (tmp > 32767) { tmp = 32767; } else { if (tmp < -32768) { tmp = -32768; } } /* Sum: '/Sum1' incorporates: * DataTypeConversion: '/Data Type Conversion1' * Product: '/Divide5' */ tmp = (((rtb_Sum1_p0 >> 16) << 1) + tmp) >> 1; if (tmp > 32767) { tmp = 32767; } else { if (tmp < -32768) { tmp = -32768; } } /* RelationalOperator: '/LowerRelop1' incorporates: * Sum: '/Sum1' */ rtb_LowerRelop1_c0 = ((int16_T)tmp > rtu_satMax); /* RelationalOperator: '/UpperRelop' incorporates: * Sum: '/Sum1' */ rtb_UpperRelop_f = ((int16_T)tmp < rtu_satMin); /* Switch: '/Switch1' incorporates: * Sum: '/Sum1' * Switch: '/Switch3' */ if (rtb_LowerRelop1_c0) { *rty_out = rtu_satMax; } else if (rtb_UpperRelop_f) { /* Switch: '/Switch3' */ *rty_out = rtu_satMin; } else { *rty_out = (int16_T)tmp; } /* End of Switch: '/Switch1' */ /* Signum: '/SignDeltaU2' incorporates: * Sum: '/Sum2' */ if (q0 < 0) { q0 = -1; } else { q0 = (q0 > 0); } /* End of Signum: '/SignDeltaU2' */ /* Signum: '/SignDeltaU3' incorporates: * Sum: '/Sum1' */ if ((int16_T)tmp < 0) { tmp_0 = -1; } else { tmp_0 = (int16_T)((int16_T)tmp > 0); } /* End of Signum: '/SignDeltaU3' */ /* Update for UnitDelay: '/UnitDelay1' incorporates: * DataTypeConversion: '/DataTypeConv4' * Logic: '/AND1' * Logic: '/AND1' * RelationalOperator: '/Equal1' */ localDW->UnitDelay1_DSTATE = ((q0 == tmp_0) && (rtb_LowerRelop1_c0 || rtb_UpperRelop_f)); /* Update for Delay: '/Resettable Delay' */ localDW->icLoad = 0U; localDW->ResettableDelay_DSTATE = rtb_Sum1_p0; } /* System initialize for atomic system: '/PI_clamp_fixdt' */ void PI_clamp_fixdt_d_Init(DW_PI_clamp_fixdt_m *localDW) { /* InitializeConditions for Delay: '/Resettable Delay' */ localDW->icLoad = 1U; } /* System reset for atomic system: '/PI_clamp_fixdt' */ void PI_clamp_fixdt_b_Reset(DW_PI_clamp_fixdt_m *localDW) { /* InitializeConditions for UnitDelay: '/UnitDelay1' */ localDW->UnitDelay1_DSTATE = false; /* InitializeConditions for Delay: '/Resettable Delay' */ localDW->icLoad = 1U; } /* Output and update for atomic system: '/PI_clamp_fixdt' */ void PI_clamp_fixdt_l(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, int16_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt_m *localDW) { boolean_T rtb_LowerRelop1_l; boolean_T rtb_UpperRelop_l; int32_T rtb_Sum1_ni; int32_T q0; int32_T tmp; int16_T tmp_0; /* Sum: '/Sum2' incorporates: * Product: '/Divide2' */ q0 = rtu_err * rtu_I; if ((q0 < 0) && (rtu_ext_limProt < MIN_int32_T - q0)) { q0 = MIN_int32_T; } else if ((q0 > 0) && (rtu_ext_limProt > MAX_int32_T - q0)) { q0 = MAX_int32_T; } else { q0 += rtu_ext_limProt; } /* Delay: '/Resettable Delay' */ if (localDW->icLoad != 0) { localDW->ResettableDelay_DSTATE = rtu_init << 16; } /* Switch: '/Switch1' incorporates: * Constant: '/Constant' * Sum: '/Sum2' * UnitDelay: '/UnitDelay1' */ if (localDW->UnitDelay1_DSTATE) { tmp = 0; } else { tmp = q0; } /* End of Switch: '/Switch1' */ /* Sum: '/Sum1' incorporates: * Delay: '/Resettable Delay' */ rtb_Sum1_ni = tmp + localDW->ResettableDelay_DSTATE; /* Product: '/Divide5' */ tmp = (rtu_err * rtu_P) >> 11; if (tmp > 32767) { tmp = 32767; } else { if (tmp < -32768) { tmp = -32768; } } /* Sum: '/Sum1' incorporates: * DataTypeConversion: '/Data Type Conversion1' * Product: '/Divide5' */ tmp = (((rtb_Sum1_ni >> 16) << 1) + tmp) >> 1; if (tmp > 32767) { tmp = 32767; } else { if (tmp < -32768) { tmp = -32768; } } /* RelationalOperator: '/LowerRelop1' incorporates: * Sum: '/Sum1' */ rtb_LowerRelop1_l = ((int16_T)tmp > rtu_satMax); /* RelationalOperator: '/UpperRelop' incorporates: * Sum: '/Sum1' */ rtb_UpperRelop_l = ((int16_T)tmp < rtu_satMin); /* Switch: '/Switch1' incorporates: * Sum: '/Sum1' * Switch: '/Switch3' */ if (rtb_LowerRelop1_l) { *rty_out = rtu_satMax; } else if (rtb_UpperRelop_l) { /* Switch: '/Switch3' */ *rty_out = rtu_satMin; } else { *rty_out = (int16_T)tmp; } /* End of Switch: '/Switch1' */ /* Signum: '/SignDeltaU2' incorporates: * Sum: '/Sum2' */ if (q0 < 0) { q0 = -1; } else { q0 = (q0 > 0); } /* End of Signum: '/SignDeltaU2' */ /* Signum: '/SignDeltaU3' incorporates: * Sum: '/Sum1' */ if ((int16_T)tmp < 0) { tmp_0 = -1; } else { tmp_0 = (int16_T)((int16_T)tmp > 0); } /* End of Signum: '/SignDeltaU3' */ /* Update for UnitDelay: '/UnitDelay1' incorporates: * DataTypeConversion: '/DataTypeConv4' * Logic: '/AND1' * Logic: '/AND1' * RelationalOperator: '/Equal1' */ localDW->UnitDelay1_DSTATE = ((q0 == tmp_0) && (rtb_LowerRelop1_l || rtb_UpperRelop_l)); /* Update for Delay: '/Resettable Delay' */ localDW->icLoad = 0U; localDW->ResettableDelay_DSTATE = rtb_Sum1_ni; } /* System initialize for atomic system: '/PI_clamp_fixdt' */ void PI_clamp_fixdt_f_Init(DW_PI_clamp_fixdt_g *localDW) { /* InitializeConditions for Delay: '/Resettable Delay' */ localDW->icLoad = 1U; } /* System reset for atomic system: '/PI_clamp_fixdt' */ void PI_clamp_fixdt_g_Reset(DW_PI_clamp_fixdt_g *localDW) { /* InitializeConditions for UnitDelay: '/UnitDelay1' */ localDW->UnitDelay1_DSTATE = false; /* InitializeConditions for Delay: '/Resettable Delay' */ localDW->icLoad = 1U; } /* Output and update for atomic system: '/PI_clamp_fixdt' */ void PI_clamp_fixdt_k(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, int16_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt_g *localDW) { boolean_T rtb_LowerRelop1_i3; boolean_T rtb_UpperRelop_i; int16_T rtb_Sum1_bm; int16_T tmp; int32_T tmp_0; int32_T q0; /* Sum: '/Sum2' incorporates: * Product: '/Divide2' */ q0 = rtu_err * rtu_I; if ((q0 < 0) && (rtu_ext_limProt < MIN_int32_T - q0)) { q0 = MIN_int32_T; } else if ((q0 > 0) && (rtu_ext_limProt > MAX_int32_T - q0)) { q0 = MAX_int32_T; } else { q0 += rtu_ext_limProt; } /* Delay: '/Resettable Delay' */ if (localDW->icLoad != 0) { localDW->ResettableDelay_DSTATE = rtu_init; } /* Switch: '/Switch1' incorporates: * Constant: '/Constant' * Sum: '/Sum2' * UnitDelay: '/UnitDelay1' */ if (localDW->UnitDelay1_DSTATE) { tmp = 0; } else { tmp = (int16_T)(((q0 < 0 ? 65535 : 0) + q0) >> 16); } /* End of Switch: '/Switch1' */ /* Sum: '/Sum1' incorporates: * Delay: '/Resettable Delay' */ rtb_Sum1_bm = (int16_T)(tmp + localDW->ResettableDelay_DSTATE); /* Product: '/Divide5' */ tmp_0 = (rtu_err * rtu_P) >> 11; if (tmp_0 > 32767) { tmp_0 = 32767; } else { if (tmp_0 < -32768) { tmp_0 = -32768; } } /* Sum: '/Sum1' incorporates: * Product: '/Divide5' */ tmp_0 = ((rtb_Sum1_bm << 1) + tmp_0) >> 1; if (tmp_0 > 32767) { tmp_0 = 32767; } else { if (tmp_0 < -32768) { tmp_0 = -32768; } } /* RelationalOperator: '/LowerRelop1' incorporates: * Sum: '/Sum1' */ rtb_LowerRelop1_i3 = ((int16_T)tmp_0 > rtu_satMax); /* RelationalOperator: '/UpperRelop' incorporates: * Sum: '/Sum1' */ rtb_UpperRelop_i = ((int16_T)tmp_0 < rtu_satMin); /* Switch: '/Switch1' incorporates: * Sum: '/Sum1' * Switch: '/Switch3' */ if (rtb_LowerRelop1_i3) { *rty_out = rtu_satMax; } else if (rtb_UpperRelop_i) { /* Switch: '/Switch3' */ *rty_out = rtu_satMin; } else { *rty_out = (int16_T)tmp_0; } /* End of Switch: '/Switch1' */ /* Signum: '/SignDeltaU2' incorporates: * Sum: '/Sum2' */ if (q0 < 0) { q0 = -1; } else { q0 = (q0 > 0); } /* End of Signum: '/SignDeltaU2' */ /* Signum: '/SignDeltaU3' incorporates: * Sum: '/Sum1' */ if ((int16_T)tmp_0 < 0) { tmp = -1; } else { tmp = (int16_T)((int16_T)tmp_0 > 0); } /* End of Signum: '/SignDeltaU3' */ /* Update for UnitDelay: '/UnitDelay1' incorporates: * DataTypeConversion: '/DataTypeConv4' * Logic: '/AND1' * Logic: '/AND1' * RelationalOperator: '/Equal1' */ localDW->UnitDelay1_DSTATE = ((q0 == tmp) && (rtb_LowerRelop1_i3 || rtb_UpperRelop_i)); /* Update for Delay: '/Resettable Delay' */ localDW->icLoad = 0U; localDW->ResettableDelay_DSTATE = rtb_Sum1_bm; } /* Model step function */ void BLDC_controller_step(RT_MODEL *const rtM) { P *rtP = ((P *) rtM->defaultParam); DW *rtDW = ((DW *) rtM->dwork); ExtU *rtU = (ExtU *) rtM->inputs; ExtY *rtY = (ExtY *) rtM->outputs; boolean_T rtb_LogicalOperator; int8_T rtb_Sum2_h; boolean_T rtb_RelationalOperator4_d; boolean_T rtb_UnitDelay5_e; uint8_T rtb_a_elecAngle_XA_g; boolean_T rtb_LogicalOperator1_j; boolean_T rtb_LogicalOperator2_p; boolean_T rtb_RelationalOperator1_mv; int16_T rtb_Switch1_l; int16_T rtb_Saturation; int16_T rtb_Saturation1; int32_T rtb_Sum1_jt; int16_T rtb_Merge_m; int16_T rtb_Merge1; int16_T rtb_TmpSignalConversionAtLow_Pa[2]; int32_T rtb_Switch1; int32_T rtb_Sum1; int32_T rtb_Gain3; uint8_T Sum; int16_T Switch2; int16_T Abs5; int16_T DataTypeConversion2; int16_T tmp[4]; int8_T UnitDelay3; /* Outputs for Atomic SubSystem: '/BLDC_controller' */ /* Sum: '/Sum' incorporates: * Gain: '/g_Ha' * Gain: '/g_Hb' * Inport: '/b_hallA ' * Inport: '/b_hallB' * Inport: '/b_hallC' */ Sum = (uint8_T)((uint32_T)(uint8_T)((uint32_T)(uint8_T)(rtU->b_hallA << 2) + (uint8_T)(rtU->b_hallB << 1)) + rtU->b_hallC); /* Logic: '/Logical Operator' incorporates: * Inport: '/b_hallA ' * Inport: '/b_hallB' * Inport: '/b_hallC' * UnitDelay: '/UnitDelay1' * UnitDelay: '/UnitDelay2' * UnitDelay: '/UnitDelay3' */ rtb_LogicalOperator = (boolean_T)((rtU->b_hallA != 0) ^ (rtU->b_hallB != 0) ^ (rtU->b_hallC != 0) ^ (rtDW->UnitDelay3_DSTATE_fy != 0) ^ (rtDW->UnitDelay1_DSTATE != 0)) ^ (rtDW->UnitDelay2_DSTATE_f != 0); /* If: '/If2' incorporates: * If: '/If2' * Inport: '/z_counterRawPrev' * UnitDelay: '/UnitDelay3' */ if (rtb_LogicalOperator) { /* Outputs for IfAction SubSystem: '/F01_03_Direction_Detection' incorporates: * ActionPort: '/Action Port' */ /* UnitDelay: '/UnitDelay3' */ UnitDelay3 = rtDW->Switch2_e; /* Sum: '/Sum2' incorporates: * Constant: '/vec_hallToPos' * Selector: '/Selector' * UnitDelay: '/UnitDelay2' */ rtb_Sum2_h = (int8_T)(rtConstP.vec_hallToPos_Value[Sum] - rtDW->UnitDelay2_DSTATE_b); /* Switch: '/Switch2' incorporates: * Constant: '/Constant20' * Constant: '/Constant23' * Constant: '/Constant24' * Constant: '/Constant8' * Logic: '/Logical Operator3' * RelationalOperator: '/Relational Operator1' * RelationalOperator: '/Relational Operator6' */ if ((rtb_Sum2_h == 1) || (rtb_Sum2_h == -5)) { rtDW->Switch2_e = 1; } else { rtDW->Switch2_e = -1; } /* End of Switch: '/Switch2' */ /* Update for UnitDelay: '/UnitDelay2' incorporates: * Constant: '/vec_hallToPos' * Selector: '/Selector' */ rtDW->UnitDelay2_DSTATE_b = rtConstP.vec_hallToPos_Value[Sum]; /* End of Outputs for SubSystem: '/F01_03_Direction_Detection' */ /* Outputs for IfAction SubSystem: '/Raw_Motor_Speed_Estimation' incorporates: * ActionPort: '/Action Port' */ rtDW->z_counterRawPrev = rtDW->UnitDelay3_DSTATE; /* Sum: '/Sum7' incorporates: * Inport: '/z_counterRawPrev' * UnitDelay: '/UnitDelay3' * UnitDelay: '/UnitDelay4' */ Switch2 = (int16_T)(rtDW->z_counterRawPrev - rtDW->UnitDelay4_DSTATE); /* Abs: '/Abs2' */ if (Switch2 < 0) { rtb_Switch1_l = (int16_T)-Switch2; } else { rtb_Switch1_l = Switch2; } /* End of Abs: '/Abs2' */ /* Relay: '/dz_cntTrnsDet' */ if (rtb_Switch1_l >= rtP->dz_cntTrnsDetHi) { rtDW->dz_cntTrnsDet_Mode = true; } else { if (rtb_Switch1_l <= rtP->dz_cntTrnsDetLo) { rtDW->dz_cntTrnsDet_Mode = false; } } rtDW->dz_cntTrnsDet = rtDW->dz_cntTrnsDet_Mode; /* End of Relay: '/dz_cntTrnsDet' */ /* RelationalOperator: '/Relational Operator4' */ rtb_RelationalOperator4_d = (rtDW->Switch2_e != UnitDelay3); /* Switch: '/Switch3' incorporates: * Constant: '/Constant4' * Logic: '/Logical Operator1' * Switch: '/Switch1' * Switch: '/Switch2' * UnitDelay: '/UnitDelay1' */ if (rtb_RelationalOperator4_d && rtDW->UnitDelay1_DSTATE_n) { rtb_Switch1_l = 0; } else if (rtb_RelationalOperator4_d) { /* Switch: '/Switch2' incorporates: * UnitDelay: '/UnitDelay4' */ rtb_Switch1_l = rtDW->UnitDelay4_DSTATE_e; } else if (rtDW->dz_cntTrnsDet) { /* Switch: '/Switch1' incorporates: * Constant: '/cf_speedCoef' * Product: '/Divide14' * Switch: '/Switch2' */ rtb_Switch1_l = (int16_T)((rtP->cf_speedCoef << 4) / rtDW->z_counterRawPrev); } else { /* Switch: '/Switch1' incorporates: * Constant: '/cf_speedCoef' * Gain: '/g_Ha' * Product: '/Divide13' * Sum: '/Sum13' * Switch: '/Switch2' * UnitDelay: '/UnitDelay2' * UnitDelay: '/UnitDelay3' * UnitDelay: '/UnitDelay5' */ rtb_Switch1_l = (int16_T)(((uint16_T)(rtP->cf_speedCoef << 2) << 4) / (int16_T)(((rtDW->UnitDelay2_DSTATE + rtDW->UnitDelay3_DSTATE_o) + rtDW->UnitDelay5_DSTATE) + rtDW->z_counterRawPrev)); } /* End of Switch: '/Switch3' */ /* Product: '/Divide11' */ rtDW->Divide11 = (int16_T)(rtb_Switch1_l * rtDW->Switch2_e); /* Update for UnitDelay: '/UnitDelay4' */ rtDW->UnitDelay4_DSTATE = rtDW->z_counterRawPrev; /* Update for UnitDelay: '/UnitDelay2' incorporates: * UnitDelay: '/UnitDelay3' */ rtDW->UnitDelay2_DSTATE = rtDW->UnitDelay3_DSTATE_o; /* Update for UnitDelay: '/UnitDelay3' incorporates: * UnitDelay: '/UnitDelay5' */ rtDW->UnitDelay3_DSTATE_o = rtDW->UnitDelay5_DSTATE; /* Update for UnitDelay: '/UnitDelay5' */ rtDW->UnitDelay5_DSTATE = rtDW->z_counterRawPrev; /* Update for UnitDelay: '/UnitDelay1' */ rtDW->UnitDelay1_DSTATE_n = rtb_RelationalOperator4_d; /* End of Outputs for SubSystem: '/Raw_Motor_Speed_Estimation' */ } /* End of If: '/If2' */ /* Outputs for Atomic SubSystem: '/Counter' */ /* Constant: '/Constant6' incorporates: * Constant: '/z_maxCntRst2' */ rtb_Switch1_l = (int16_T) Counter(1, rtP->z_maxCntRst, rtb_LogicalOperator, &rtDW->Counter_e); /* End of Outputs for SubSystem: '/Counter' */ /* Switch: '/Switch2' incorporates: * Constant: '/Constant4' * Constant: '/z_maxCntRst' * RelationalOperator: '/Relational Operator2' */ if (rtb_Switch1_l > rtP->z_maxCntRst) { Switch2 = 0; } else { Switch2 = rtDW->Divide11; } /* End of Switch: '/Switch2' */ /* Abs: '/Abs5' */ if (Switch2 < 0) { Abs5 = (int16_T)-Switch2; } else { Abs5 = Switch2; } /* End of Abs: '/Abs5' */ /* Relay: '/n_commDeacv' */ if (Abs5 >= rtP->n_commDeacvHi) { rtDW->n_commDeacv_Mode = true; } else { if (Abs5 <= rtP->n_commAcvLo) { rtDW->n_commDeacv_Mode = false; } } /* Logic: '/Logical Operator3' incorporates: * Constant: '/b_angleMeasEna' * Logic: '/Logical Operator1' * Logic: '/Logical Operator2' * Relay: '/n_commDeacv' */ rtb_LogicalOperator = (rtP->b_angleMeasEna || (rtDW->n_commDeacv_Mode && (!rtDW->dz_cntTrnsDet))); /* UnitDelay: '/UnitDelay2' */ rtb_RelationalOperator4_d = rtDW->UnitDelay2_DSTATE_c; /* UnitDelay: '/UnitDelay5' */ rtb_UnitDelay5_e = rtDW->UnitDelay5_DSTATE_m; /* DataTypeConversion: '/Data Type Conversion2' incorporates: * Inport: '/r_inpTgt' */ DataTypeConversion2 = (int16_T)(rtU->r_inpTgt << 4); /* Saturate: '/Saturation' incorporates: * Inport: '/i_phaAB' */ rtb_Gain3 = rtU->i_phaAB << 4; if (rtb_Gain3 >= 27200) { rtb_Saturation = 27200; } else if (rtb_Gain3 <= -27200) { rtb_Saturation = -27200; } else { rtb_Saturation = (int16_T)(rtU->i_phaAB << 4); } /* End of Saturate: '/Saturation' */ /* Saturate: '/Saturation1' incorporates: * Inport: '/i_phaBC' */ rtb_Gain3 = rtU->i_phaBC << 4; if (rtb_Gain3 >= 27200) { rtb_Saturation1 = 27200; } else if (rtb_Gain3 <= -27200) { rtb_Saturation1 = -27200; } else { rtb_Saturation1 = (int16_T)(rtU->i_phaBC << 4); } /* End of Saturate: '/Saturation1' */ /* If: '/If1' incorporates: * Constant: '/b_angleMeasEna' */ if (!rtP->b_angleMeasEna) { /* Outputs for IfAction SubSystem: '/F01_05_Electrical_Angle_Estimation' incorporates: * ActionPort: '/Action Port' */ /* Switch: '/Switch2' incorporates: * Constant: '/Constant16' * Product: '/Divide1' * Product: '/Divide3' * RelationalOperator: '/Relational Operator7' * Sum: '/Sum3' * Switch: '/Switch3' */ if (rtb_LogicalOperator) { /* MinMax: '/MinMax' */ rtb_Merge_m = rtb_Switch1_l; if (!(rtb_Merge_m < rtDW->z_counterRawPrev)) { rtb_Merge_m = rtDW->z_counterRawPrev; } /* End of MinMax: '/MinMax' */ /* Switch: '/Switch3' incorporates: * Constant: '/vec_hallToPos' * Constant: '/Constant16' * RelationalOperator: '/Relational Operator7' * Selector: '/Selector' * Sum: '/Sum1' */ if (rtDW->Switch2_e == 1) { rtb_Sum2_h = rtConstP.vec_hallToPos_Value[Sum]; } else { rtb_Sum2_h = (int8_T)(rtConstP.vec_hallToPos_Value[Sum] + 1); } rtb_Merge_m = (int16_T)(((int16_T)((int16_T)((rtb_Merge_m << 14) / rtDW->z_counterRawPrev) * rtDW->Switch2_e) + (rtb_Sum2_h << 14)) >> 2); } else { if (rtDW->Switch2_e == 1) { /* Switch: '/Switch3' incorporates: * Constant: '/vec_hallToPos' * Selector: '/Selector' */ rtb_Sum2_h = rtConstP.vec_hallToPos_Value[Sum]; } else { /* Switch: '/Switch3' incorporates: * Constant: '/vec_hallToPos' * Selector: '/Selector' * Sum: '/Sum1' */ rtb_Sum2_h = (int8_T)(rtConstP.vec_hallToPos_Value[Sum] + 1); } rtb_Merge_m = (int16_T)(rtb_Sum2_h << 12); } /* End of Switch: '/Switch2' */ /* MinMax: '/MinMax1' incorporates: * Constant: '/Constant1' */ if (!(rtb_Merge_m > 0)) { rtb_Merge_m = 0; } /* End of MinMax: '/MinMax1' */ /* SignalConversion: '/Signal Conversion2' incorporates: * Product: '/Divide2' */ rtb_Merge_m = (int16_T)((15 * rtb_Merge_m) >> 4); /* End of Outputs for SubSystem: '/F01_05_Electrical_Angle_Estimation' */ } else { /* Outputs for IfAction SubSystem: '/F01_06_Electrical_Angle_Measurement' incorporates: * ActionPort: '/Action Port' */ /* Sum: '/Sum1' incorporates: * Constant: '/Constant2' * Constant: '/n_polePairs' * Inport: '/a_mechAngle' * Product: '/Divide' */ rtb_Sum1_jt = rtU->a_mechAngle * rtP->n_polePairs - 480; /* DataTypeConversion: '/Data Type Conversion20' incorporates: * Constant: '/a_elecPeriod' * Product: '/Divide2' * Product: '/Divide3' * Sum: '/Sum3' */ rtb_Merge_m = (int16_T)((int16_T)(rtb_Sum1_jt - ((int16_T)((int16_T) div_nde_s32_floor(rtb_Sum1_jt, 5760) * 360) << 4)) << 2); /* End of Outputs for SubSystem: '/F01_06_Electrical_Angle_Measurement' */ } /* End of If: '/If1' */ /* If: '