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Updated current limit 

The firmware allows now to set higher currents than 15 A/motor.
NOTE: You can change this limit at your own risk. I do not take any responsability if your boards gets damaged.
This commit is contained in:
EmanuelFeru 2019-11-03 12:45:13 +01:00
parent 0fb080ad1b
commit 9a9eed7d10
9 changed files with 83 additions and 79 deletions
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01_Matlab/03_CreateParamTable/tableParamType.xlsx
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01_Matlab/BLDCmotorControl_FOC_R2017b_fixdt.slx
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7
01_Matlab/init_model.m
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@ -138,10 +138,11 @@ cf_iqKpLimProt = 7.2; % [-] Current limit protection gain (onl
cf_iqKiLimProt = 40.7 / f_ctrl; % [-] Current limit protection integral gain (only used in SPD_MODE) cf_iqKiLimProt = 40.7 / f_ctrl; % [-] Current limit protection integral gain (only used in SPD_MODE)
i_max = 15; % [A] Maximum allowed motor current (continuous) i_max = 15; % [A] Maximum allowed motor current (continuous)
i_max = i_max * i_sca; i_max = i_max * i_sca;
iq_max_XA = 0:15:i_max; iq_maxSca_XA = 0:0.02:0.99;
iq_max_M1 = sqrt(i_max^2 - iq_max_XA.^2); % Current circle limitations map iq_maxSca_XA = fixpt_evenspace_cleanup(iq_maxSca_XA, ufix(16), 2^-16); % Make sure the data is evely spaced up to the last bit
iq_maxSca_M1 = sqrt(1 - iq_maxSca_XA.^2); % Current circle limitations map
% figure % figure
% stairs(iq_max_XA, iq_max_M1); legend('i_{max}'); % stairs(iq_maxSca_XA, iq_maxSca_M1); legend('i_{maxSca}');
%------------------------------- %-------------------------------
%% F05_Control_Type_Management %% F05_Control_Type_Management

15
Inc/BLDC_controller.h
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@ -3,9 +3,9 @@
* *
* Code generated for Simulink model 'BLDC_controller'. * Code generated for Simulink model 'BLDC_controller'.
* *
* Model version : 1.1197 * Model version : 1.1199
* Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017
* C/C++ source code generated on : Thu Oct 31 21:29:42 2019 * C/C++ source code generated on : Sun Nov 3 12:28:16 2019
* *
* Target selection: ert.tlc * Target selection: ert.tlc
* Embedded hardware selection: ARM Compatible->ARM Cortex * Embedded hardware selection: ARM Compatible->ARM Cortex
@ -139,6 +139,11 @@ typedef struct {
*/ */
int16_T r_cos_M1_Table[181]; int16_T r_cos_M1_Table[181];
/* Computed Parameter: iq_maxSca_M1_Table
* Referenced by: '<S35>/iq_maxSca_M1'
*/
uint16_T iq_maxSca_M1_Table[50];
/* Computed Parameter: vec_hallToPos_Value /* Computed Parameter: vec_hallToPos_Value
* Referenced by: '<S9>/vec_hallToPos' * Referenced by: '<S9>/vec_hallToPos'
*/ */
@ -229,12 +234,6 @@ struct P_ {
int16_T id_fieldWeak_M1[12]; /* Variable: id_fieldWeak_M1 int16_T id_fieldWeak_M1[12]; /* Variable: id_fieldWeak_M1
* Referenced by: '<S32>/id_fieldWeak_M1' * Referenced by: '<S32>/id_fieldWeak_M1'
*/ */
int16_T iq_max_M1[51]; /* Variable: iq_max_M1
* Referenced by: '<S35>/iq_max_M1'
*/
int16_T iq_max_XA[51]; /* Variable: iq_max_XA
* Referenced by: '<S35>/iq_max_XA'
*/
int16_T n_commAcvLo; /* Variable: n_commAcvLo int16_T n_commAcvLo; /* Variable: n_commAcvLo
* Referenced by: '<S11>/n_commDeacv' * Referenced by: '<S11>/n_commDeacv'
*/ */

109
Src/BLDC_controller.c
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@ -3,9 +3,9 @@
* *
* Code generated for Simulink model 'BLDC_controller'. * Code generated for Simulink model 'BLDC_controller'.
* *
* Model version : 1.1197 * Model version : 1.1199
* Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017
* C/C++ source code generated on : Thu Oct 31 21:29:42 2019 * C/C++ source code generated on : Sun Nov 3 12:28:16 2019
* *
* Target selection: ert.tlc * Target selection: ert.tlc
* Embedded hardware selection: ARM Compatible->ARM Cortex * Embedded hardware selection: ARM Compatible->ARM Cortex
@ -856,11 +856,11 @@ void BLDC_controller_step(RT_MODEL *const rtM)
* Inport: '<Root>/r_inpTgt' * Inport: '<Root>/r_inpTgt'
*/ */
if (rtb_Gain3 >= 16000) { if (rtb_Gain3 >= 16000) {
rtb_Gain4 = 16000; rtb_toNegative = 16000;
} else if (rtb_Gain3 <= -16000) { } else if (rtb_Gain3 <= -16000) {
rtb_Gain4 = -16000; rtb_toNegative = -16000;
} else { } else {
rtb_Gain4 = (int16_T)(rtU->r_inpTgt << 4); rtb_toNegative = (int16_T)(rtU->r_inpTgt << 4);
} }
/* Outputs for IfAction SubSystem: '<S7>/FOC_Control_Type' incorporates: /* Outputs for IfAction SubSystem: '<S7>/FOC_Control_Type' incorporates:
@ -872,7 +872,7 @@ void BLDC_controller_step(RT_MODEL *const rtM)
* Selector: '<S14>/Selector' * Selector: '<S14>/Selector'
*/ */
rtb_Merge = (int16_T)(((uint16_T)((tmp[rtU->z_ctrlModReq] << 5) / 125) * rtb_Merge = (int16_T)(((uint16_T)((tmp[rtU->z_ctrlModReq] << 5) / 125) *
rtb_Gain4) >> 12); rtb_toNegative) >> 12);
/* End of Outputs for SubSystem: '<S7>/FOC_Control_Type' */ /* End of Outputs for SubSystem: '<S7>/FOC_Control_Type' */
} else if (rtb_Gain3 >= 16000) { } else if (rtb_Gain3 >= 16000) {
@ -1199,15 +1199,15 @@ void BLDC_controller_step(RT_MODEL *const rtM)
/* Abs: '<S3>/Abs4' incorporates: /* Abs: '<S3>/Abs4' incorporates:
* UnitDelay: '<S6>/UnitDelay4' * UnitDelay: '<S6>/UnitDelay4'
*/ */
rtb_Gain4 = (int16_T)-rtDW->UnitDelay4_DSTATE; rtb_toNegative = (int16_T)-rtDW->UnitDelay4_DSTATE;
} else { } else {
/* Abs: '<S3>/Abs4' incorporates: /* Abs: '<S3>/Abs4' incorporates:
* UnitDelay: '<S6>/UnitDelay4' * UnitDelay: '<S6>/UnitDelay4'
*/ */
rtb_Gain4 = rtDW->UnitDelay4_DSTATE; rtb_toNegative = rtDW->UnitDelay4_DSTATE;
} }
rtb_RelationalOperator1_m = ((rtb_Gain4 > rtP->r_errInpTgtThres) && rtb_RelationalOperator1_m = ((rtb_toNegative > rtP->r_errInpTgtThres) &&
rtb_RelationalOperator4_d); rtb_RelationalOperator4_d);
} }
@ -1830,43 +1830,49 @@ void BLDC_controller_step(RT_MODEL *const rtM)
/* Abs: '<S35>/Abs5' */ /* Abs: '<S35>/Abs5' */
if (rtDW->Switch1 < 0) { if (rtDW->Switch1 < 0) {
rtb_Gain4 = (int16_T)-rtDW->Switch1; rtb_toNegative = (int16_T)-rtDW->Switch1;
} else { } else {
rtb_Gain4 = rtDW->Switch1; rtb_toNegative = rtDW->Switch1;
} }
/* End of Abs: '<S35>/Abs5' */ /* End of Abs: '<S35>/Abs5' */
/* PreLookup: '<S35>/Vq_max_XA' */ /* PreLookup: '<S35>/Vq_max_XA' */
rtb_r_fieldWeak_XA_o1 = plook_u8s16_evencka(rtb_Gain4, rtP->Vq_max_XA[0], rtb_r_fieldWeak_XA_o1 = plook_u8s16_evencka(rtb_toNegative, rtP->Vq_max_XA[0],
(uint16_T)(rtP->Vq_max_XA[1] - rtP->Vq_max_XA[0]), 45U); (uint16_T)(rtP->Vq_max_XA[1] - rtP->Vq_max_XA[0]), 45U);
/* Interpolation_n-D: '<S35>/Vq_max_M1' */
rtb_Gain2_f = rtP->Vq_max_M1[rtb_r_fieldWeak_XA_o1];
/* Gain: '<S35>/Gain5' incorporates: /* Gain: '<S35>/Gain5' incorporates:
* Interpolation_n-D: '<S35>/Vq_max_M1' * Interpolation_n-D: '<S35>/Vq_max_M1'
*/ */
rtb_Saturation = (int16_T)-rtP->Vq_max_M1[rtb_r_fieldWeak_XA_o1]; rtb_Gain2_f = (int16_T)-rtP->Vq_max_M1[rtb_r_fieldWeak_XA_o1];
/* PreLookup: '<S35>/iq_max_XA' */ /* Interpolation_n-D: '<S35>/iq_maxSca_M1' incorporates:
rtb_r_fieldWeak_XA_o1 = plook_u8s16_evencka(rtb_id_fieldWeak_M1,
rtP->iq_max_XA[0], (uint16_T)(rtP->iq_max_XA[1] - rtP->iq_max_XA[0]), 50U);
/* MinMax: '<S35>/MinMax' incorporates:
* Constant: '<S35>/i_max' * Constant: '<S35>/i_max'
* Interpolation_n-D: '<S35>/iq_max_M1' * Product: '<S35>/Divide4'
*/ */
if (rtP->i_max < rtP->iq_max_M1[rtb_r_fieldWeak_XA_o1]) { rtb_Gain3 = rtb_id_fieldWeak_M1 << 16;
rtb_id_fieldWeak_M1 = rtP->i_max; rtb_Gain3 = (rtb_Gain3 == MIN_int32_T) && (rtP->i_max == -1) ? MAX_int32_T :
rtb_Gain3 / rtP->i_max;
if (rtb_Gain3 < 0) {
rtb_Gain3 = 0;
} else { } else {
rtb_id_fieldWeak_M1 = rtP->iq_max_M1[rtb_r_fieldWeak_XA_o1]; if (rtb_Gain3 > 65535) {
rtb_Gain3 = 65535;
}
} }
/* End of MinMax: '<S35>/MinMax' */ /* Product: '<S35>/Divide1' incorporates:
* Constant: '<S35>/i_max'
* Interpolation_n-D: '<S35>/iq_maxSca_M1'
* PreLookup: '<S35>/iq_maxSca_XA'
* Product: '<S35>/Divide4'
*/
rtb_id_fieldWeak_M1 = (int16_T)
((rtConstP.iq_maxSca_M1_Table[plook_u8u16_evencka((uint16_T)rtb_Gain3, 0U,
1311U, 49U)] * rtP->i_max) >> 16);
/* Gain: '<S35>/Gain1' */ /* Gain: '<S35>/Gain1' */
rtb_toNegative = (int16_T)-rtb_id_fieldWeak_M1; rtb_Saturation = (int16_T)-rtb_id_fieldWeak_M1;
/* If: '<S35>/If1' incorporates: /* If: '<S35>/If1' incorporates:
* Constant: '<S35>/CTRL_COMM' * Constant: '<S35>/CTRL_COMM'
@ -1897,12 +1903,12 @@ void BLDC_controller_step(RT_MODEL *const rtM)
* Switch: '<S47>/Switch' * Switch: '<S47>/Switch'
*/ */
if (rtDW->Sum1[0] > rtb_id_fieldWeak_M1) { if (rtDW->Sum1[0] > rtb_id_fieldWeak_M1) {
rtb_Gain4 = rtb_id_fieldWeak_M1; rtb_toNegative = rtb_id_fieldWeak_M1;
} else if (rtDW->Sum1[0] < rtb_toNegative) { } else if (rtDW->Sum1[0] < rtb_Saturation) {
/* Switch: '<S47>/Switch' */ /* Switch: '<S47>/Switch' */
rtb_Gain4 = rtb_toNegative; rtb_toNegative = rtb_Saturation;
} else { } else {
rtb_Gain4 = rtDW->Sum1[0]; rtb_toNegative = rtDW->Sum1[0];
} }
/* End of Switch: '<S47>/Switch2' */ /* End of Switch: '<S47>/Switch2' */
@ -1911,8 +1917,8 @@ void BLDC_controller_step(RT_MODEL *const rtM)
* Constant: '<S45>/cf_iqKpLimProt' * Constant: '<S45>/cf_iqKpLimProt'
* Sum: '<S45>/Sum3' * Sum: '<S45>/Sum3'
*/ */
rtb_Gain3 = ((int16_T)(rtb_Gain4 - rtDW->Sum1[0]) * rtP->cf_iqKpLimProt) >> rtb_Gain3 = ((int16_T)(rtb_toNegative - rtDW->Sum1[0]) *
8; rtP->cf_iqKpLimProt) >> 8;
if (rtb_Gain3 > 32767) { if (rtb_Gain3 > 32767) {
rtb_Gain3 = 32767; rtb_Gain3 = 32767;
} else { } else {
@ -1932,7 +1938,7 @@ void BLDC_controller_step(RT_MODEL *const rtM)
/* Gain: '<S35>/Gain6' incorporates: /* Gain: '<S35>/Gain6' incorporates:
* Constant: '<S35>/n_max1' * Constant: '<S35>/n_max1'
*/ */
rtb_Gain4 = (int16_T)-rtP->n_max; rtb_toNegative = (int16_T)-rtP->n_max;
/* If: '<S35>/If2' incorporates: /* If: '<S35>/If2' incorporates:
* Constant: '<S35>/CTRL_COMM2' * Constant: '<S35>/CTRL_COMM2'
@ -1964,10 +1970,10 @@ void BLDC_controller_step(RT_MODEL *const rtM)
* Switch: '<S48>/Switch' * Switch: '<S48>/Switch'
*/ */
if (rtb_Switch2_fv > rtP->n_max) { if (rtb_Switch2_fv > rtP->n_max) {
rtb_Gain4 = rtP->n_max; rtb_toNegative = rtP->n_max;
} else { } else {
if (!(rtb_Switch2_fv < rtb_Gain4)) { if (!(rtb_Switch2_fv < rtb_toNegative)) {
rtb_Gain4 = rtb_Switch2_fv; rtb_toNegative = rtb_Switch2_fv;
} }
} }
@ -1977,8 +1983,8 @@ void BLDC_controller_step(RT_MODEL *const rtM)
* Constant: '<S46>/cf_nKpLimProt' * Constant: '<S46>/cf_nKpLimProt'
* Sum: '<S46>/Sum1' * Sum: '<S46>/Sum1'
*/ */
rtb_Gain3 = ((int16_T)(rtb_Gain4 - rtb_Switch2_fv) * rtP->cf_nKpLimProt) >> rtb_Gain3 = ((int16_T)(rtb_toNegative - rtb_Switch2_fv) *
8; rtP->cf_nKpLimProt) >> 8;
if (rtb_Gain3 > 32767) { if (rtb_Gain3 > 32767) {
rtb_Gain3 = 32767; rtb_Gain3 = 32767;
} else { } else {
@ -1999,6 +2005,7 @@ void BLDC_controller_step(RT_MODEL *const rtM)
* Constant: '<S38>/cf_iqKiLimProt' * Constant: '<S38>/cf_iqKiLimProt'
* Constant: '<S38>/cf_nKi' * Constant: '<S38>/cf_nKi'
* Constant: '<S38>/cf_nKp' * Constant: '<S38>/cf_nKp'
* Interpolation_n-D: '<S35>/Vq_max_M1'
* Product: '<S38>/Divide1' * Product: '<S38>/Divide1'
* SignalConversion: '<S38>/Signal Conversion2' * SignalConversion: '<S38>/Signal Conversion2'
* Sum: '<S38>/Sum3' * Sum: '<S38>/Sum3'
@ -2039,19 +2046,20 @@ void BLDC_controller_step(RT_MODEL *const rtM)
} }
/* Switch: '<S67>/Switch2' incorporates: /* Switch: '<S67>/Switch2' incorporates:
* Interpolation_n-D: '<S35>/Vq_max_M1'
* RelationalOperator: '<S67>/LowerRelop1' * RelationalOperator: '<S67>/LowerRelop1'
* RelationalOperator: '<S67>/UpperRelop' * RelationalOperator: '<S67>/UpperRelop'
* Sum: '<S41>/Sum3' * Sum: '<S41>/Sum3'
* Switch: '<S67>/Switch' * Switch: '<S67>/Switch'
*/ */
if ((int16_T)rtb_Gain3 > rtb_Gain2_f) { if ((int16_T)rtb_Gain3 > rtP->Vq_max_M1[rtb_r_fieldWeak_XA_o1]) {
/* SignalConversion: '<S41>/Signal Conversion2' */ /* SignalConversion: '<S41>/Signal Conversion2' */
rtDW->Merge = rtb_Gain2_f; rtDW->Merge = rtP->Vq_max_M1[rtb_r_fieldWeak_XA_o1];
} else if ((int16_T)rtb_Gain3 < rtb_Saturation) { } else if ((int16_T)rtb_Gain3 < rtb_Gain2_f) {
/* Switch: '<S67>/Switch' incorporates: /* Switch: '<S67>/Switch' incorporates:
* SignalConversion: '<S41>/Signal Conversion2' * SignalConversion: '<S41>/Signal Conversion2'
*/ */
rtDW->Merge = rtb_Saturation; rtDW->Merge = rtb_Gain2_f;
} else { } else {
/* SignalConversion: '<S41>/Signal Conversion2' */ /* SignalConversion: '<S41>/Signal Conversion2' */
rtDW->Merge = (int16_T)rtb_Gain3; rtDW->Merge = (int16_T)rtb_Gain3;
@ -2092,8 +2100,9 @@ void BLDC_controller_step(RT_MODEL *const rtM)
/* Outputs for Atomic SubSystem: '<S38>/PI_clamp_fixdt_n' */ /* Outputs for Atomic SubSystem: '<S38>/PI_clamp_fixdt_n' */
rtDW->Merge = (int16_T) PI_clamp_fixdt_n((int16_T)rtb_Gain3, rtP->cf_nKp, rtDW->Merge = (int16_T) PI_clamp_fixdt_n((int16_T)rtb_Gain3, rtP->cf_nKp,
rtP->cf_nKi, rtb_Gain2_f, rtb_Saturation, (int16_T)((rtDW->Divide4 * rtP->cf_nKi, rtP->Vq_max_M1[rtb_r_fieldWeak_XA_o1], rtb_Gain2_f,
rtP->cf_iqKiLimProt) >> 10), &rtDW->PI_clamp_fixdt_n_o); (int16_T)((rtDW->Divide4 * rtP->cf_iqKiLimProt) >> 10),
&rtDW->PI_clamp_fixdt_n_o);
/* End of Outputs for SubSystem: '<S38>/PI_clamp_fixdt_n' */ /* End of Outputs for SubSystem: '<S38>/PI_clamp_fixdt_n' */
@ -2137,8 +2146,8 @@ void BLDC_controller_step(RT_MODEL *const rtM)
/* Switch: '<S58>/Switch' incorporates: /* Switch: '<S58>/Switch' incorporates:
* RelationalOperator: '<S58>/UpperRelop' * RelationalOperator: '<S58>/UpperRelop'
*/ */
if ((int16_T)rtb_Gain3 < rtb_toNegative) { if ((int16_T)rtb_Gain3 < rtb_Saturation) {
rtb_id_fieldWeak_M1 = rtb_toNegative; rtb_id_fieldWeak_M1 = rtb_Saturation;
} else { } else {
rtb_id_fieldWeak_M1 = (int16_T)rtb_Gain3; rtb_id_fieldWeak_M1 = (int16_T)rtb_Gain3;
} }
@ -2164,10 +2173,12 @@ void BLDC_controller_step(RT_MODEL *const rtM)
* Constant: '<S39>/cf_iqKi' * Constant: '<S39>/cf_iqKi'
* Constant: '<S39>/cf_iqKp' * Constant: '<S39>/cf_iqKp'
* Constant: '<S39>/constant' * Constant: '<S39>/constant'
* Interpolation_n-D: '<S35>/Vq_max_M1'
* Sum: '<S39>/Sum1' * Sum: '<S39>/Sum1'
*/ */
PI_clamp_fixdt((int16_T)rtb_Gain3, rtP->cf_iqKp, rtP->cf_iqKi, rtb_Gain2_f, PI_clamp_fixdt((int16_T)rtb_Gain3, rtP->cf_iqKp, rtP->cf_iqKi,
rtb_Saturation, 0, &rtDW->Merge, &rtDW->PI_clamp_fixdt_iq); rtP->Vq_max_M1[rtb_r_fieldWeak_XA_o1], rtb_Gain2_f, 0,
&rtDW->Merge, &rtDW->PI_clamp_fixdt_iq);
/* End of Outputs for SubSystem: '<S39>/PI_clamp_fixdt_iq' */ /* End of Outputs for SubSystem: '<S39>/PI_clamp_fixdt_iq' */

31
Src/BLDC_controller_data.c
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@ -3,9 +3,9 @@
* *
* Code generated for Simulink model 'BLDC_controller'. * Code generated for Simulink model 'BLDC_controller'.
* *
* Model version : 1.1197 * Model version : 1.1199
* Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017
* C/C++ source code generated on : Thu Oct 31 21:29:42 2019 * C/C++ source code generated on : Sun Nov 3 12:28:16 2019
* *
* Target selection: ert.tlc * Target selection: ert.tlc
* Embedded hardware selection: ARM Compatible->ARM Cortex * Embedded hardware selection: ARM Compatible->ARM Cortex
@ -68,6 +68,16 @@ const ConstP rtConstP = {
16135, 16225, 16294, 16344, 16374, 16384, 16374, 16344, 16294, 16225, 16135, 16135, 16225, 16294, 16344, 16374, 16384, 16374, 16344, 16294, 16225, 16135,
16026, 15897, 15749, 15582, 15396, 15191, 14968, 14726, 14466, 14189 }, 16026, 15897, 15749, 15582, 15396, 15191, 14968, 14726, 14466, 14189 },
/* Computed Parameter: iq_maxSca_M1_Table
* Referenced by: '<S35>/iq_maxSca_M1'
*/
{ 65535U, 65523U, 65484U, 65418U, 65326U, 65207U, 65062U, 64890U, 64691U,
64465U, 64211U, 63930U, 63620U, 63281U, 62913U, 62516U, 62088U, 61630U,
61140U, 60618U, 60062U, 59473U, 58848U, 58187U, 57489U, 56752U, 55974U,
55155U, 54291U, 53381U, 52422U, 51413U, 50349U, 49227U, 48043U, 46792U,
45470U, 44069U, 42581U, 40997U, 39307U, 37494U, 35541U, 33422U, 31105U,
28540U, 25655U, 22323U, 18304U, 12974U },
/* Computed Parameter: vec_hallToPos_Value /* Computed Parameter: vec_hallToPos_Value
* Referenced by: '<S9>/vec_hallToPos' * Referenced by: '<S9>/vec_hallToPos'
*/ */
@ -170,23 +180,6 @@ P rtP_Left = {
*/ */
{ 0, 80, 240, 560, 1040, 1680, 2400, 3040, 3520, 3840, 4000, 4000 }, { 0, 80, 240, 560, 1040, 1680, 2400, 3040, 3520, 3840, 4000, 4000 },
/* Variable: iq_max_M1
* Referenced by: '<S35>/iq_max_M1'
*/
{ 12000, 11998, 11990, 11978, 11962, 11940, 11913, 11882, 11845, 11804, 11758,
11706, 11649, 11587, 11520, 11447, 11369, 11285, 11195, 11100, 10998, 10890,
10776, 10655, 10527, 10392, 10250, 10100, 9942, 9775, 9600, 9415, 9220, 9015,
8799, 8570, 8328, 8071, 7799, 7509, 7200, 6868, 6511, 6124, 5700, 5231, 4703,
4094, 3360, 2388, 0 },
/* Variable: iq_max_XA
* Referenced by: '<S35>/iq_max_XA'
*/
{ 0, 240, 480, 720, 960, 1200, 1440, 1680, 1920, 2160, 2400, 2640, 2880, 3120,
3360, 3600, 3840, 4080, 4320, 4560, 4800, 5040, 5280, 5520, 5760, 6000, 6240,
6480, 6720, 6960, 7200, 7440, 7680, 7920, 8160, 8400, 8640, 8880, 9120, 9360,
9600, 9840, 10080, 10320, 10560, 10800, 11040, 11280, 11520, 11760, 12000 },
/* Variable: n_commAcvLo /* Variable: n_commAcvLo
* Referenced by: '<S11>/n_commDeacv' * Referenced by: '<S11>/n_commDeacv'
*/ */

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