From 4991a15a5ed3c4a32cf4ae5e8cebe346fd4a0e45 Mon Sep 17 00:00:00 2001 From: EmanuelFeru Date: Tue, 20 Oct 2020 17:49:40 +0200 Subject: [PATCH] Fixed bug PI controller integrator is now working correctly. --- Inc/BLDC_controller.h | 593 ++--- Inc/rtwtypes.h | 4 +- Src/BLDC_controller.c | 4533 +++++++++++++++++++----------------- Src/BLDC_controller_data.c | 202 +- 4 files changed, 2744 insertions(+), 2588 deletions(-) diff --git a/Inc/BLDC_controller.h b/Inc/BLDC_controller.h index 264222a..73f7876 100644 --- a/Inc/BLDC_controller.h +++ b/Inc/BLDC_controller.h @@ -3,9 +3,9 @@ * * Code generated for Simulink model 'BLDC_controller'. * - * Model version : 1.1284 + * Model version : 1.1296 * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 - * C/C++ source code generated on : Sun Oct 11 21:38:56 2020 + * C/C++ source code generated on : Tue Oct 20 17:29:57 2020 * * Target selection: ert.tlc * Embedded hardware selection: ARM Compatible->ARM Cortex @@ -30,167 +30,174 @@ /* Forward declaration for rtModel */ typedef struct tag_RTM RT_MODEL; -/* Block signals and states (auto storage) for system '/Counter' */ +/* Block signals and states (auto storage) for system '/Counter' */ typedef struct { - int16_T UnitDelay_DSTATE; /* '/UnitDelay' */ + int16_T UnitDelay_DSTATE; /* '/UnitDelay' */ } DW_Counter; -/* Block signals and states (auto storage) for system '/PI_clamp_fixdt' */ +/* Block signals and states (auto storage) for system '/Low_Pass_Filter' */ typedef struct { - int32_T ResettableDelay_DSTATE; /* '/Resettable Delay' */ - uint8_T icLoad; /* '/Resettable Delay' */ - boolean_T UnitDelay1_DSTATE; /* '/UnitDelay1' */ -} DW_PI_clamp_fixdt; - -/* Block signals and states (auto storage) for system '/PI_clamp_fixdt' */ -typedef struct { - int32_T ResettableDelay_DSTATE; /* '/Resettable Delay' */ - uint8_T icLoad; /* '/Resettable Delay' */ - boolean_T UnitDelay1_DSTATE; /* '/UnitDelay1' */ -} DW_PI_clamp_fixdt_i; - -/* Block signals and states (auto storage) for system '/PI_clamp_fixdt' */ -typedef struct { - int16_T ResettableDelay_DSTATE; /* '/Resettable Delay' */ - uint8_T icLoad; /* '/Resettable Delay' */ - boolean_T UnitDelay1_DSTATE; /* '/UnitDelay1' */ -} DW_PI_clamp_fixdt_e; - -/* Block signals and states (auto storage) for system '/Low_Pass_Filter' */ -typedef struct { - int32_T UnitDelay1_DSTATE[2]; /* '/UnitDelay1' */ + int32_T UnitDelay1_DSTATE[2]; /* '/UnitDelay1' */ } DW_Low_Pass_Filter; -/* Block signals and states (auto storage) for system '/I_backCalc_fixdt' */ +/* Block signals and states (auto storage) for system '/Counter' */ typedef struct { - int32_T UnitDelay_DSTATE; /* '/UnitDelay' */ - int32_T UnitDelay_DSTATE_h; /* '/UnitDelay' */ -} DW_I_backCalc_fixdt; + uint16_T UnitDelay_DSTATE; /* '/UnitDelay' */ +} DW_Counter_b; -/* Block signals and states (auto storage) for system '/Counter' */ +/* Block signals and states (auto storage) for system '/either_edge' */ typedef struct { - uint16_T UnitDelay_DSTATE; /* '/UnitDelay' */ -} DW_Counter_l; - -/* Block signals and states (auto storage) for system '/either_edge' */ -typedef struct { - boolean_T UnitDelay_DSTATE; /* '/UnitDelay' */ + boolean_T UnitDelay_DSTATE; /* '/UnitDelay' */ } DW_either_edge; -/* Block signals and states (auto storage) for system '/Debounce_Filter' */ +/* Block signals and states (auto storage) for system '/Debounce_Filter' */ typedef struct { - DW_either_edge either_edge_k; /* '/either_edge' */ - DW_Counter_l Counter_h; /* '/Counter' */ - DW_Counter_l Counter_i0; /* '/Counter' */ - boolean_T UnitDelay_DSTATE; /* '/UnitDelay' */ + DW_either_edge either_edge_p; /* '/either_edge' */ + DW_Counter_b Counter_e; /* '/Counter' */ + DW_Counter_b Counter_n1; /* '/Counter' */ + boolean_T UnitDelay_DSTATE; /* '/UnitDelay' */ } DW_Debounce_Filter; +/* Block signals and states (auto storage) for system '/I_backCalc_fixdt' */ +typedef struct { + int32_T UnitDelay_DSTATE; /* '/UnitDelay' */ + int32_T UnitDelay_DSTATE_m; /* '/UnitDelay' */ +} DW_I_backCalc_fixdt; + +/* Block signals and states (auto storage) for system '/PI_clamp_fixdt' */ +typedef struct { + int32_T ResettableDelay_DSTATE; /* '/Resettable Delay' */ + uint8_T icLoad; /* '/Resettable Delay' */ + boolean_T UnitDelay1_DSTATE; /* '/UnitDelay1' */ +} DW_PI_clamp_fixdt; + +/* Block signals and states (auto storage) for system '/PI_clamp_fixdt' */ +typedef struct { + int32_T ResettableDelay_DSTATE; /* '/Resettable Delay' */ + uint8_T icLoad; /* '/Resettable Delay' */ + boolean_T UnitDelay1_DSTATE; /* '/UnitDelay1' */ +} DW_PI_clamp_fixdt_m; + +/* Block signals and states (auto storage) for system '/PI_clamp_fixdt' */ +typedef struct { + int16_T ResettableDelay_DSTATE; /* '/Resettable Delay' */ + uint8_T icLoad; /* '/Resettable Delay' */ + boolean_T UnitDelay1_DSTATE; /* '/UnitDelay1' */ +} DW_PI_clamp_fixdt_g; + /* Block signals and states (auto storage) for system '' */ typedef struct { - DW_either_edge either_edge_a; /* '/either_edge' */ - DW_Debounce_Filter Debounce_Filter_f;/* '/Debounce_Filter' */ - DW_I_backCalc_fixdt I_backCalc_fixdt_g;/* '/I_backCalc_fixdt' */ - DW_I_backCalc_fixdt I_backCalc_fixdt1;/* '/I_backCalc_fixdt1' */ - DW_I_backCalc_fixdt I_backCalc_fixdt_i;/* '/I_backCalc_fixdt' */ - DW_Low_Pass_Filter Low_Pass_Filter_m;/* '/Low_Pass_Filter' */ - DW_PI_clamp_fixdt_e PI_clamp_fixdt_at;/* '/PI_clamp_fixdt' */ - DW_PI_clamp_fixdt_i PI_clamp_fixdt_oc;/* '/PI_clamp_fixdt' */ - DW_PI_clamp_fixdt PI_clamp_fixdt_k; /* '/PI_clamp_fixdt' */ - DW_Counter Counter_e; /* '/Counter' */ - int32_T Divide1; /* '/Divide1' */ - int32_T UnitDelay_DSTATE; /* '/UnitDelay' */ - int16_T Gain4[3]; /* '/Gain4' */ - int16_T DataTypeConversion[2]; /* '/Data Type Conversion' */ - int16_T z_counterRawPrev; /* '/z_counterRawPrev' */ - int16_T Merge1; /* '/Merge1' */ - int16_T Divide3; /* '/Divide3' */ - int16_T Vd_max1; /* '/Vd_max1' */ - int16_T Gain3; /* '/Gain3' */ - int16_T Vq_max_M1; /* '/Vq_max_M1' */ - int16_T Gain5; /* '/Gain5' */ - int16_T i_max; /* '/i_max' */ - int16_T Divide1_a; /* '/Divide1' */ - int16_T Gain1; /* '/Gain1' */ - int16_T Gain4_c; /* '/Gain4' */ - int16_T Switch2; /* '/Switch2' */ - int16_T Switch2_l; /* '/Switch2' */ - int16_T Switch2_c; /* '/Switch2' */ - int16_T Merge; /* '/Merge' */ - int16_T Switch1; /* '/Switch1' */ - int16_T Divide11; /* '/Divide11' */ - int16_T UnitDelay3_DSTATE; /* '/UnitDelay3' */ - int16_T UnitDelay4_DSTATE; /* '/UnitDelay4' */ - int16_T UnitDelay2_DSTATE; /* '/UnitDelay2' */ - int16_T UnitDelay3_DSTATE_o; /* '/UnitDelay3' */ - int16_T UnitDelay5_DSTATE; /* '/UnitDelay5' */ - int16_T UnitDelay4_DSTATE_e; /* '/UnitDelay4' */ - int16_T UnitDelay4_DSTATE_eu; /* '/UnitDelay4' */ - int16_T UnitDelay4_DSTATE_h; /* '/UnitDelay4' */ - int8_T Switch2_e; /* '/Switch2' */ - int8_T UnitDelay2_DSTATE_b; /* '/UnitDelay2' */ - int8_T If4_ActiveSubsystem; /* '/If4' */ - int8_T If1_ActiveSubsystem; /* '/If1' */ - int8_T If2_ActiveSubsystem; /* '/If2' */ - int8_T If2_ActiveSubsystem_a; /* '/If2' */ - int8_T If1_ActiveSubsystem_e; /* '/If1' */ - int8_T SwitchCase_ActiveSubsystem; /* '/Switch Case' */ - uint8_T z_ctrlMod; /* '/F03_02_Control_Mode_Manager' */ - uint8_T UnitDelay3_DSTATE_fy; /* '/UnitDelay3' */ - uint8_T UnitDelay1_DSTATE; /* '/UnitDelay1' */ - uint8_T UnitDelay2_DSTATE_f; /* '/UnitDelay2' */ - uint8_T is_active_c1_BLDC_controller;/* '/F03_02_Control_Mode_Manager' */ - uint8_T is_c1_BLDC_controller; /* '/F03_02_Control_Mode_Manager' */ - uint8_T is_ACTIVE; /* '/F03_02_Control_Mode_Manager' */ - boolean_T Merge_n; /* '/Merge' */ - boolean_T dz_cntTrnsDet; /* '/dz_cntTrnsDet' */ - boolean_T UnitDelay2_DSTATE_g; /* '/UnitDelay2' */ - boolean_T UnitDelay5_DSTATE_l; /* '/UnitDelay5' */ - boolean_T UnitDelay6_DSTATE; /* '/UnitDelay6' */ - boolean_T UnitDelay_DSTATE_b; /* '/UnitDelay' */ - boolean_T UnitDelay1_DSTATE_n; /* '/UnitDelay1' */ - boolean_T n_commDeacv_Mode; /* '/n_commDeacv' */ - boolean_T dz_cntTrnsDet_Mode; /* '/dz_cntTrnsDet' */ + DW_PI_clamp_fixdt_g PI_clamp_fixdt_kh;/* '/PI_clamp_fixdt' */ + DW_PI_clamp_fixdt_m PI_clamp_fixdt_l4;/* '/PI_clamp_fixdt' */ + DW_PI_clamp_fixdt PI_clamp_fixdt_i; /* '/PI_clamp_fixdt' */ + DW_I_backCalc_fixdt I_backCalc_fixdt_j;/* '/I_backCalc_fixdt' */ + DW_I_backCalc_fixdt I_backCalc_fixdt1;/* '/I_backCalc_fixdt1' */ + DW_I_backCalc_fixdt I_backCalc_fixdt_i;/* '/I_backCalc_fixdt' */ + DW_either_edge either_edge_i; /* '/either_edge' */ + DW_Debounce_Filter Debounce_Filter_k;/* '/Debounce_Filter' */ + DW_Low_Pass_Filter Low_Pass_Filter_m;/* '/Low_Pass_Filter' */ + DW_Counter Counter_e; /* '/Counter' */ + int32_T Divide1; /* '/Divide1' */ + int32_T UnitDelay_DSTATE; /* '/UnitDelay' */ + int16_T Gain4_e[3]; /* '/Gain4' */ + int16_T DataTypeConversion[2]; /* '/Data Type Conversion' */ + int16_T z_counterRawPrev; /* '/z_counterRawPrev' */ + int16_T Merge; /* '/Merge' */ + int16_T Switch1; /* '/Switch1' */ + int16_T Vd_max1; /* '/Vd_max1' */ + int16_T Gain3; /* '/Gain3' */ + int16_T Vq_max_M1; /* '/Vq_max_M1' */ + int16_T Gain5; /* '/Gain5' */ + int16_T i_max; /* '/i_max' */ + int16_T Divide1_n; /* '/Divide1' */ + int16_T Gain1; /* '/Gain1' */ + int16_T Gain4; /* '/Gain4' */ + int16_T Switch2_i; /* '/Switch2' */ + int16_T Switch2_o; /* '/Switch2' */ + int16_T Switch2_a; /* '/Switch2' */ + int16_T Divide3; /* '/Divide3' */ + int16_T Merge1; /* '/Merge1' */ + int16_T Abs1; /* '/Abs1' */ + int16_T Abs5_h; /* '/Abs5' */ + int16_T Divide11; /* '/Divide11' */ + int16_T r_sin_M1; /* '/r_sin_M1' */ + int16_T r_cos_M1; /* '/r_cos_M1' */ + int16_T UnitDelay3_DSTATE; /* '/UnitDelay3' */ + int16_T UnitDelay4_DSTATE; /* '/UnitDelay4' */ + int16_T UnitDelay2_DSTATE; /* '/UnitDelay2' */ + int16_T UnitDelay3_DSTATE_o; /* '/UnitDelay3' */ + int16_T UnitDelay5_DSTATE; /* '/UnitDelay5' */ + int16_T UnitDelay4_DSTATE_e; /* '/UnitDelay4' */ + int16_T UnitDelay4_DSTATE_eu; /* '/UnitDelay4' */ + int8_T Switch2_e; /* '/Switch2' */ + int8_T UnitDelay2_DSTATE_b; /* '/UnitDelay2' */ + int8_T If1_ActiveSubsystem; /* '/If1' */ + int8_T If2_ActiveSubsystem; /* '/If2' */ + int8_T If1_ActiveSubsystem_j; /* '/If1' */ + int8_T SwitchCase_ActiveSubsystem; /* '/Switch Case' */ + int8_T If1_ActiveSubsystem_a; /* '/If1' */ + int8_T If1_ActiveSubsystem_o; /* '/If1' */ + int8_T SwitchCase_ActiveSubsystem_d; /* '/Switch Case' */ + int8_T If2_ActiveSubsystem_f; /* '/If2' */ + int8_T If2_ActiveSubsystem_a; /* '/If2' */ + uint8_T z_ctrlMod; /* '/F03_02_Control_Mode_Manager' */ + uint8_T UnitDelay3_DSTATE_fy; /* '/UnitDelay3' */ + uint8_T UnitDelay1_DSTATE; /* '/UnitDelay1' */ + uint8_T UnitDelay2_DSTATE_f; /* '/UnitDelay2' */ + uint8_T UnitDelay_DSTATE_e; /* '/UnitDelay' */ + uint8_T is_active_c1_BLDC_controller;/* '/F03_02_Control_Mode_Manager' */ + uint8_T is_c1_BLDC_controller; /* '/F03_02_Control_Mode_Manager' */ + uint8_T is_ACTIVE; /* '/F03_02_Control_Mode_Manager' */ + boolean_T Merge_p; /* '/Merge' */ + boolean_T dz_cntTrnsDet; /* '/dz_cntTrnsDet' */ + boolean_T UnitDelay2_DSTATE_c; /* '/UnitDelay2' */ + boolean_T UnitDelay5_DSTATE_m; /* '/UnitDelay5' */ + boolean_T UnitDelay6_DSTATE; /* '/UnitDelay6' */ + boolean_T UnitDelay_DSTATE_b; /* '/UnitDelay' */ + boolean_T UnitDelay1_DSTATE_n; /* '/UnitDelay1' */ + boolean_T n_commDeacv_Mode; /* '/n_commDeacv' */ + boolean_T dz_cntTrnsDet_Mode; /* '/dz_cntTrnsDet' */ } DW; /* Constant parameters (auto storage) */ typedef struct { - /* Computed Parameter: r_sin3PhaA_M1_Table - * Referenced by: '/r_sin3PhaA_M1' - */ - int16_T r_sin3PhaA_M1_Table[181]; - - /* Computed Parameter: r_sin3PhaB_M1_Table - * Referenced by: '/r_sin3PhaB_M1' - */ - int16_T r_sin3PhaB_M1_Table[181]; - - /* Computed Parameter: r_sin3PhaC_M1_Table - * Referenced by: '/r_sin3PhaC_M1' - */ - int16_T r_sin3PhaC_M1_Table[181]; - /* Computed Parameter: r_sin_M1_Table - * Referenced by: '/r_sin_M1' + * Referenced by: '/r_sin_M1' */ int16_T r_sin_M1_Table[181]; /* Computed Parameter: r_cos_M1_Table - * Referenced by: '/r_cos_M1' + * Referenced by: '/r_cos_M1' */ int16_T r_cos_M1_Table[181]; + /* Computed Parameter: r_sin3PhaA_M1_Table + * Referenced by: '/r_sin3PhaA_M1' + */ + int16_T r_sin3PhaA_M1_Table[181]; + + /* Computed Parameter: r_sin3PhaB_M1_Table + * Referenced by: '/r_sin3PhaB_M1' + */ + int16_T r_sin3PhaB_M1_Table[181]; + + /* Computed Parameter: r_sin3PhaC_M1_Table + * Referenced by: '/r_sin3PhaC_M1' + */ + int16_T r_sin3PhaC_M1_Table[181]; + /* Computed Parameter: iq_maxSca_M1_Table - * Referenced by: '/iq_maxSca_M1' + * Referenced by: '/iq_maxSca_M1' */ uint16_T iq_maxSca_M1_Table[50]; /* Computed Parameter: z_commutMap_M1_table - * Referenced by: '/z_commutMap_M1' + * Referenced by: '/z_commutMap_M1' */ int8_T z_commutMap_M1_table[18]; /* Computed Parameter: vec_hallToPos_Value - * Referenced by: '/vec_hallToPos' + * Referenced by: '/vec_hallToPos' */ int8_T vec_hallToPos_Value[8]; } ConstP; @@ -224,145 +231,145 @@ typedef struct { /* Parameters (auto storage) */ struct P_ { int32_T dV_openRate; /* Variable: dV_openRate - * Referenced by: '/dV_openRate' + * Referenced by: '/dV_openRate' */ int16_T dz_cntTrnsDetHi; /* Variable: dz_cntTrnsDetHi - * Referenced by: '/dz_cntTrnsDet' + * Referenced by: '/dz_cntTrnsDet' */ int16_T dz_cntTrnsDetLo; /* Variable: dz_cntTrnsDetLo - * Referenced by: '/dz_cntTrnsDet' + * Referenced by: '/dz_cntTrnsDet' */ int16_T n_cruiseMotTgt; /* Variable: n_cruiseMotTgt - * Referenced by: '/n_cruiseMotTgt' + * Referenced by: '/n_cruiseMotTgt' */ int16_T z_maxCntRst; /* Variable: z_maxCntRst * Referenced by: - * '/Counter' - * '/z_maxCntRst' - * '/z_maxCntRst2' - * '/UnitDelay3' - * '/z_counter' + * '/Counter' + * '/z_maxCntRst' + * '/z_maxCntRst2' + * '/UnitDelay3' + * '/z_counter' */ uint16_T cf_speedCoef; /* Variable: cf_speedCoef - * Referenced by: '/cf_speedCoef' + * Referenced by: '/cf_speedCoef' */ uint16_T t_errDequal; /* Variable: t_errDequal - * Referenced by: '/t_errDequal' + * Referenced by: '/t_errDequal' */ uint16_T t_errQual; /* Variable: t_errQual - * Referenced by: '/t_errQual' + * Referenced by: '/t_errQual' */ int16_T Vd_max; /* Variable: Vd_max * Referenced by: - * '/Vd_max1' - * '/Vd_max' + * '/Vd_max' + * '/Vd_max1' */ int16_T Vq_max_M1[46]; /* Variable: Vq_max_M1 - * Referenced by: '/Vq_max_M1' + * Referenced by: '/Vq_max_M1' */ int16_T Vq_max_XA[46]; /* Variable: Vq_max_XA - * Referenced by: '/Vq_max_XA' + * Referenced by: '/Vq_max_XA' */ int16_T a_phaAdvMax; /* Variable: a_phaAdvMax - * Referenced by: '/a_phaAdvMax' + * Referenced by: '/a_phaAdvMax' */ int16_T i_max; /* Variable: i_max * Referenced by: - * '/i_max' - * '/i_max' + * '/i_max' + * '/i_max' */ int16_T id_fieldWeakMax; /* Variable: id_fieldWeakMax - * Referenced by: '/id_fieldWeakMax' + * Referenced by: '/id_fieldWeakMax' */ int16_T n_commAcvLo; /* Variable: n_commAcvLo - * Referenced by: '/n_commDeacv' + * Referenced by: '/n_commDeacv' */ int16_T n_commDeacvHi; /* Variable: n_commDeacvHi - * Referenced by: '/n_commDeacv' + * Referenced by: '/n_commDeacv' */ int16_T n_fieldWeakAuthHi; /* Variable: n_fieldWeakAuthHi - * Referenced by: '/n_fieldWeakAuthHi' + * Referenced by: '/n_fieldWeakAuthHi' */ int16_T n_fieldWeakAuthLo; /* Variable: n_fieldWeakAuthLo - * Referenced by: '/n_fieldWeakAuthLo' + * Referenced by: '/n_fieldWeakAuthLo' */ int16_T n_max; /* Variable: n_max * Referenced by: - * '/n_max1' - * '/n_max' + * '/n_max' + * '/n_max1' */ int16_T n_stdStillDet; /* Variable: n_stdStillDet - * Referenced by: '/n_stdStillDet' + * Referenced by: '/n_stdStillDet' */ int16_T r_errInpTgtThres; /* Variable: r_errInpTgtThres - * Referenced by: '/r_errInpTgtThres' + * Referenced by: '/r_errInpTgtThres' */ int16_T r_fieldWeakHi; /* Variable: r_fieldWeakHi - * Referenced by: '/r_fieldWeakHi' + * Referenced by: '/r_fieldWeakHi' */ int16_T r_fieldWeakLo; /* Variable: r_fieldWeakLo - * Referenced by: '/r_fieldWeakLo' + * Referenced by: '/r_fieldWeakLo' */ uint16_T cf_KbLimProt; /* Variable: cf_KbLimProt * Referenced by: - * '/cf_KbLimProt' - * '/cf_KbLimProt' + * '/cf_KbLimProt' + * '/cf_KbLimProt' */ uint16_T cf_idKp; /* Variable: cf_idKp - * Referenced by: '/cf_idKp1' + * Referenced by: '/cf_idKp1' */ uint16_T cf_iqKp; /* Variable: cf_iqKp - * Referenced by: '/cf_iqKp' + * Referenced by: '/cf_iqKp' */ uint16_T cf_nKp; /* Variable: cf_nKp - * Referenced by: '/cf_nKp' + * Referenced by: '/cf_nKp' */ uint16_T cf_currFilt; /* Variable: cf_currFilt - * Referenced by: '/cf_currFilt' + * Referenced by: '/cf_currFilt' */ uint16_T cf_idKi; /* Variable: cf_idKi - * Referenced by: '/cf_idKi1' + * Referenced by: '/cf_idKi1' */ uint16_T cf_iqKi; /* Variable: cf_iqKi - * Referenced by: '/cf_iqKi' + * Referenced by: '/cf_iqKi' */ uint16_T cf_iqKiLimProt; /* Variable: cf_iqKiLimProt * Referenced by: - * '/cf_iqKiLimProt' - * '/cf_iqKiLimProt' + * '/cf_iqKiLimProt' + * '/cf_iqKiLimProt' */ uint16_T cf_nKi; /* Variable: cf_nKi - * Referenced by: '/cf_nKi' + * Referenced by: '/cf_nKi' */ uint16_T cf_nKiLimProt; /* Variable: cf_nKiLimProt * Referenced by: - * '/cf_nKiLimProt' - * '/cf_nKiLimProt' + * '/cf_nKiLimProt' + * '/cf_nKiLimProt' */ uint8_T n_polePairs; /* Variable: n_polePairs - * Referenced by: '/n_polePairs' + * Referenced by: '/n_polePairs' */ uint8_T z_ctrlTypSel; /* Variable: z_ctrlTypSel * Referenced by: '/z_ctrlTypSel' */ uint8_T z_selPhaCurMeasABC; /* Variable: z_selPhaCurMeasABC - * Referenced by: '/z_selPhaCurMeasABC' + * Referenced by: '/z_selPhaCurMeasABC' */ boolean_T b_angleMeasEna; /* Variable: b_angleMeasEna * Referenced by: - * '/b_angleMeasEna' - * '/b_angleMeasEna' + * '/b_angleMeasEna' + * '/b_angleMeasEna' */ boolean_T b_cruiseCtrlEna; /* Variable: b_cruiseCtrlEna * Referenced by: '/b_cruiseCtrlEna' */ boolean_T b_diagEna; /* Variable: b_diagEna - * Referenced by: '/b_diagEna' + * Referenced by: '/b_diagEna' */ boolean_T b_fieldWeakEna; /* Variable: b_fieldWeakEna * Referenced by: - * '/b_fieldWeakEna' - * '/b_fieldWeakEna' + * '/b_fieldWeakEna' + * '/b_fieldWeakEna' */ }; @@ -387,33 +394,34 @@ extern void BLDC_controller_step(RT_MODEL *const rtM); /*- * These blocks were eliminated from the model due to optimizations: * - * Block '/Scope2' : Unused code path elimination - * Block '/Scope' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Scope2' : Unused code path elimination + * Block '/Scope' : Unused code path elimination * Block '/Data Type Duplicate' : Unused code path elimination * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination * Block '/Data Type Duplicate' : Unused code path elimination * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Data Type Duplicate' : Unused code path elimination - * Block '/Data Type Propagation' : Unused code path elimination - * Block '/Scope12' : Unused code path elimination - * Block '/Scope8' : Unused code path elimination - * Block '/Scope' : Unused code path elimination - * Block '/Data Type Conversion1' : Eliminate redundant data type conversion - * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Scope12' : Unused code path elimination + * Block '/Scope8' : Unused code path elimination + * Block '/toNegative' : Unused code path elimination + * Block '/Scope' : Unused code path elimination + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion */ /*- @@ -435,96 +443,103 @@ extern void BLDC_controller_step(RT_MODEL *const rtM); * * '' : 'BLDCmotor_FOC_R2017b_fixdt' * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Weakening' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F06_Control_Type_Management' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/Task_Scheduler' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_01_Edge_Detector' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_02_Position_Calculation' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_03_Direction_Detection' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_04_Speed_Estimation' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_05_Electrical_Angle_Estimation' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_06_Electrical_Angle_Measurement' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_04_Speed_Estimation/Counter' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_04_Speed_Estimation/Raw_Motor_Speed_Estimation' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_04_Speed_Estimation/Counter/rst_Delay' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_06_Electrical_Angle_Measurement/Modulo_fixdt' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Debounce_Filter' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/either_edge' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Debounce_Filter/Default' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Debounce_Filter/Dequalification' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Debounce_Filter/Qualification' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Debounce_Filter/either_edge' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Debounce_Filter/Dequalification/Counter' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Debounce_Filter/Dequalification/Counter/rst_Delay' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Debounce_Filter/Qualification/Counter' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Debounce_Filter/Qualification/Counter/rst_Delay' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_01_Mode_Transition_Calculation' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_02_Control_Mode_Manager' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Default_Control_Type' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Default_Mode' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/FOC_Control_Type' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Open_Mode' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Open_Mode/Rate_Limiter' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Open_Mode/rising_edge_init' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Open_Mode/Rate_Limiter/Delay_Init1' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Open_Mode/Rate_Limiter/Saturation Dynamic' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Weakening/Saturation Dynamic' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Weakening/Saturation Dynamic1' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Transform' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Current_Filtering' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Inv_Clarke_Transform' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Inv_Park_Transform' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Park_Transform' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Sine_Cosine_Approximation' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Transform/Clarke_PhasesAB' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Transform/Clarke_PhasesAC' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Transform/Clarke_PhasesBC' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Current_Filtering/Low_Pass_Filter' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Open_Mode' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Speed_Mode' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Torque_Mode' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Vd_Calculation' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Voltage_Mode' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Speed_Mode/PI_clamp_fixdt' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Speed_Mode/PI_clamp_fixdt/Clamping_circuit' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Speed_Mode/PI_clamp_fixdt/Integrator' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Speed_Mode/PI_clamp_fixdt/Saturation_hit' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Torque_Mode/PI_clamp_fixdt' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Torque_Mode/Saturation Dynamic1' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Torque_Mode/PI_clamp_fixdt/Clamping_circuit' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Torque_Mode/PI_clamp_fixdt/Integrator' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Torque_Mode/PI_clamp_fixdt/Saturation_hit' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Vd_Calculation/PI_clamp_fixdt' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Vd_Calculation/Saturation Dynamic' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Vd_Calculation/PI_clamp_fixdt/Clamping_circuit' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Vd_Calculation/PI_clamp_fixdt/Integrator' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Vd_Calculation/PI_clamp_fixdt/Saturation_hit' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/Voltage_Mode/Saturation Dynamic1' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Speed_Mode_Protection' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Torque_Mode_Protection' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Voltage_Mode_Protection' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Speed_Mode_Protection/Saturation Dynamic' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Torque_Mode_Protection/I_backCalc_fixdt' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Torque_Mode_Protection/I_backCalc_fixdt/Integrator' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Torque_Mode_Protection/I_backCalc_fixdt/Saturation Dynamic1' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Voltage_Mode_Protection/I_backCalc_fixdt' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Voltage_Mode_Protection/I_backCalc_fixdt1' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Voltage_Mode_Protection/I_backCalc_fixdt/Integrator' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Voltage_Mode_Protection/I_backCalc_fixdt/Saturation Dynamic1' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Voltage_Mode_Protection/I_backCalc_fixdt1/Integrator' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Voltage_Mode_Protection/I_backCalc_fixdt1/Saturation Dynamic1' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F06_Control_Type_Management/COM_Method' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F06_Control_Type_Management/FOC_Method' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F06_Control_Type_Management/SIN_Method' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F06_Control_Type_Management/SIN_Method/Final_Phase_Advance_Calculation' - * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F06_Control_Type_Management/SIN_Method/Final_Phase_Advance_Calculation/Modulo_fixdt' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/Call_Scheduler' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Weakening' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F06_Control_Type_Management' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/Task_Scheduler' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_01_Edge_Detector' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_02_Position_Calculation' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_03_Direction_Detection' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_04_Speed_Estimation' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_05_Electrical_Angle_Estimation' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_06_Electrical_Angle_Measurement' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_04_Speed_Estimation/Counter' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_04_Speed_Estimation/Raw_Motor_Speed_Estimation' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_04_Speed_Estimation/Counter/rst_Delay' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F01_Estimations/F01_06_Electrical_Angle_Measurement/Modulo_fixdt' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Diagnostics_Enabled' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Diagnostics_Enabled/Debounce_Filter' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Diagnostics_Enabled/either_edge' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Diagnostics_Enabled/Debounce_Filter/Default' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Diagnostics_Enabled/Debounce_Filter/Dequalification' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Diagnostics_Enabled/Debounce_Filter/Qualification' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Diagnostics_Enabled/Debounce_Filter/either_edge' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Diagnostics_Enabled/Debounce_Filter/Dequalification/Counter' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Diagnostics_Enabled/Debounce_Filter/Dequalification/Counter/rst_Delay' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Diagnostics_Enabled/Debounce_Filter/Qualification/Counter' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F02_Diagnostics/Diagnostics_Enabled/Debounce_Filter/Qualification/Counter/rst_Delay' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_01_Mode_Transition_Calculation' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_02_Control_Mode_Manager' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Default_Control_Type' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Default_Mode' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/FOC_Control_Type' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Open_Mode' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Open_Mode/Rate_Limiter' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Open_Mode/rising_edge_init' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Open_Mode/Rate_Limiter/Delay_Init1' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F03_Control_Mode_Manager/F03_03_Input_Target_Synthesis/Open_Mode/Rate_Limiter/Saturation Dynamic' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Weakening/Field_Weakening_Enabled' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Weakening/Field_Weakening_Enabled/Saturation Dynamic' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F04_Field_Weakening/Field_Weakening_Enabled/Saturation Dynamic1' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Park_Transform_Forward' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Park_Transform_Inverse' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Park_Transform_Forward/Clarke_Transform' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Park_Transform_Forward/Current_Filtering' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Park_Transform_Forward/Park_Transform' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Park_Transform_Forward/Sine_Cosine_Approximation' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Park_Transform_Forward/Clarke_Transform/Clarke_PhasesAB' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Park_Transform_Forward/Clarke_Transform/Clarke_PhasesAC' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Park_Transform_Forward/Clarke_Transform/Clarke_PhasesBC' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Park_Transform_Forward/Current_Filtering/Low_Pass_Filter' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Park_Transform_Inverse/Inv_Clarke_Transform' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Clarke_Park_Transform_Inverse/Inv_Park_Transform' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Open_Mode' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Speed_Mode' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Torque_Mode' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Vd_Calculation' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Voltage_Mode' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Speed_Mode/PI_clamp_fixdt' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Speed_Mode/PI_clamp_fixdt/Clamping_circuit' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Speed_Mode/PI_clamp_fixdt/Integrator' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Speed_Mode/PI_clamp_fixdt/Saturation_hit' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Torque_Mode/PI_clamp_fixdt' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Torque_Mode/Saturation Dynamic1' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Torque_Mode/PI_clamp_fixdt/Clamping_circuit' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Torque_Mode/PI_clamp_fixdt/Integrator' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Torque_Mode/PI_clamp_fixdt/Saturation_hit' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Vd_Calculation/PI_clamp_fixdt' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Vd_Calculation/Saturation Dynamic' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Vd_Calculation/PI_clamp_fixdt/Clamping_circuit' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Vd_Calculation/PI_clamp_fixdt/Integrator' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Vd_Calculation/PI_clamp_fixdt/Saturation_hit' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/FOC/FOC_Enabled/Voltage_Mode/Saturation Dynamic1' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Speed_Mode_Protection' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Torque_Mode_Protection' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Voltage_Mode_Protection' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Speed_Mode_Protection/Saturation Dynamic' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Torque_Mode_Protection/I_backCalc_fixdt' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Torque_Mode_Protection/I_backCalc_fixdt/Integrator' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Torque_Mode_Protection/I_backCalc_fixdt/Saturation Dynamic1' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Voltage_Mode_Protection/I_backCalc_fixdt' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Voltage_Mode_Protection/I_backCalc_fixdt1' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Voltage_Mode_Protection/I_backCalc_fixdt/Integrator' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Voltage_Mode_Protection/I_backCalc_fixdt/Saturation Dynamic1' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Voltage_Mode_Protection/I_backCalc_fixdt1/Integrator' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F05_Field_Oriented_Control/Motor_Limitations/Motor_Limitations_Enabled/Voltage_Mode_Protection/I_backCalc_fixdt1/Saturation Dynamic1' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F06_Control_Type_Management/COM_Method' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F06_Control_Type_Management/FOC_Method' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F06_Control_Type_Management/SIN_Method' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F06_Control_Type_Management/SIN_Method/Final_Phase_Advance_Calculation' + * '' : 'BLDCmotor_FOC_R2017b_fixdt/BLDC_controller/F06_Control_Type_Management/SIN_Method/Final_Phase_Advance_Calculation/Modulo_fixdt' */ #endif /* RTW_HEADER_BLDC_controller_h_ */ diff --git a/Inc/rtwtypes.h b/Inc/rtwtypes.h index 49ec197..e6b2250 100644 --- a/Inc/rtwtypes.h +++ b/Inc/rtwtypes.h @@ -3,9 +3,9 @@ * * Code generated for Simulink model 'BLDC_controller'. * - * Model version : 1.1284 + * Model version : 1.1296 * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 - * C/C++ source code generated on : Sun Oct 11 21:38:56 2020 + * C/C++ source code generated on : Tue Oct 20 17:29:57 2020 * * Target selection: ert.tlc * Embedded hardware selection: ARM Compatible->ARM Cortex diff --git a/Src/BLDC_controller.c b/Src/BLDC_controller.c index 2028911..439c623 100644 --- a/Src/BLDC_controller.c +++ b/Src/BLDC_controller.c @@ -3,9 +3,9 @@ * * Code generated for Simulink model 'BLDC_controller'. * - * Model version : 1.1284 + * Model version : 1.1296 * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 - * C/C++ source code generated on : Sun Oct 11 21:38:56 2020 + * C/C++ source code generated on : Tue Oct 20 17:29:57 2020 * * Target selection: ert.tlc * Embedded hardware selection: ARM Compatible->ARM Cortex @@ -19,7 +19,7 @@ #include "BLDC_controller.h" -/* Named constants for Chart: '/F03_02_Control_Mode_Manager' */ +/* Named constants for Chart: '/F03_02_Control_Mode_Manager' */ #define IN_ACTIVE ((uint8_T)1U) #define IN_NO_ACTIVE_CHILD ((uint8_T)0U) #define IN_OPEN ((uint8_T)2U) @@ -101,35 +101,39 @@ int32_T div_nde_s32_floor(int32_T numerator, int32_T denominator); extern void Counter_Init(DW_Counter *localDW, int16_T rtp_z_cntInit); extern int16_T Counter(int16_T rtu_inc, int16_T rtu_max, boolean_T rtu_rst, DW_Counter *localDW); -extern void PI_clamp_fixdt_Init(DW_PI_clamp_fixdt *localDW); -extern void PI_clamp_fixdt(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, - int32_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T - rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt *localDW); -extern void PI_clamp_fixdt_g_Init(DW_PI_clamp_fixdt_i *localDW); -extern void PI_clamp_fixdt_g_Reset(DW_PI_clamp_fixdt_i *localDW); -extern int16_T PI_clamp_fixdt_o(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, - int16_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T - rtu_ext_limProt, DW_PI_clamp_fixdt_i *localDW); -extern void PI_clamp_fixdt_k_Init(DW_PI_clamp_fixdt_e *localDW); -extern void PI_clamp_fixdt_b_Reset(DW_PI_clamp_fixdt_e *localDW); -extern int16_T PI_clamp_fixdt_a(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, - int16_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T - rtu_ext_limProt, DW_PI_clamp_fixdt_e *localDW); extern void Low_Pass_Filter_Reset(DW_Low_Pass_Filter *localDW); extern void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T rty_y[2], DW_Low_Pass_Filter *localDW); +extern void Counter_b_Init(DW_Counter_b *localDW, uint16_T rtp_z_cntInit); +extern void Counter_n(uint16_T rtu_inc, uint16_T rtu_max, boolean_T rtu_rst, + uint16_T *rty_cnt, DW_Counter_b *localDW); +extern void either_edge(boolean_T rtu_u, boolean_T *rty_y, DW_either_edge + *localDW); +extern void Debounce_Filter_Init(DW_Debounce_Filter *localDW); +extern void Debounce_Filter(boolean_T rtu_u, uint16_T rtu_tAcv, uint16_T + rtu_tDeacv, boolean_T *rty_y, DW_Debounce_Filter *localDW); extern void I_backCalc_fixdt_Init(DW_I_backCalc_fixdt *localDW, int32_T rtp_yInit); +extern void I_backCalc_fixdt_Reset(DW_I_backCalc_fixdt *localDW, int32_T + rtp_yInit); extern void I_backCalc_fixdt(int16_T rtu_err, uint16_T rtu_I, uint16_T rtu_Kb, int16_T rtu_satMax, int16_T rtu_satMin, int16_T *rty_out, DW_I_backCalc_fixdt * localDW); -extern void Counter_b_Init(DW_Counter_l *localDW, uint16_T rtp_z_cntInit); -extern uint16_T Counter_i(uint16_T rtu_inc, uint16_T rtu_max, boolean_T rtu_rst, - DW_Counter_l *localDW); -extern boolean_T either_edge(boolean_T rtu_u, DW_either_edge *localDW); -extern void Debounce_Filter_Init(DW_Debounce_Filter *localDW); -extern void Debounce_Filter(boolean_T rtu_u, uint16_T rtu_tAcv, uint16_T - rtu_tDeacv, boolean_T *rty_y, DW_Debounce_Filter *localDW); +extern void PI_clamp_fixdt_Init(DW_PI_clamp_fixdt *localDW); +extern void PI_clamp_fixdt_Reset(DW_PI_clamp_fixdt *localDW); +extern void PI_clamp_fixdt(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, + int32_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T + rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt *localDW); +extern void PI_clamp_fixdt_d_Init(DW_PI_clamp_fixdt_m *localDW); +extern void PI_clamp_fixdt_b_Reset(DW_PI_clamp_fixdt_m *localDW); +extern void PI_clamp_fixdt_l(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, + int16_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T + rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt_m *localDW); +extern void PI_clamp_fixdt_f_Init(DW_PI_clamp_fixdt_g *localDW); +extern void PI_clamp_fixdt_g_Reset(DW_PI_clamp_fixdt_g *localDW); +extern void PI_clamp_fixdt_k(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, + int16_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T + rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt_g *localDW); uint8_T plook_u8s16_evencka(int16_T u, int16_T bp0, uint16_T bpSpace, uint32_T maxIndex) { @@ -190,23 +194,23 @@ int32_T div_nde_s32_floor(int32_T numerator, int32_T denominator) 0) ? -1 : 0) + numerator / denominator; } -/* System initialize for atomic system: '/Counter' */ +/* System initialize for atomic system: '/Counter' */ void Counter_Init(DW_Counter *localDW, int16_T rtp_z_cntInit) { - /* InitializeConditions for UnitDelay: '/UnitDelay' */ + /* InitializeConditions for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = rtp_z_cntInit; } -/* Output and update for atomic system: '/Counter' */ +/* Output and update for atomic system: '/Counter' */ int16_T Counter(int16_T rtu_inc, int16_T rtu_max, boolean_T rtu_rst, DW_Counter * localDW) { int16_T rtu_rst_0; int16_T rty_cnt_0; - /* Switch: '/Switch1' incorporates: - * Constant: '/Constant23' - * UnitDelay: '/UnitDelay' + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant23' + * UnitDelay: '/UnitDelay' */ if (rtu_rst) { rtu_rst_0 = 0; @@ -214,478 +218,40 @@ int16_T Counter(int16_T rtu_inc, int16_T rtu_max, boolean_T rtu_rst, DW_Counter rtu_rst_0 = localDW->UnitDelay_DSTATE; } - /* End of Switch: '/Switch1' */ + /* End of Switch: '/Switch1' */ - /* Sum: '/Sum1' */ + /* Sum: '/Sum1' */ rty_cnt_0 = (int16_T)(rtu_inc + rtu_rst_0); - /* MinMax: '/MinMax' */ + /* MinMax: '/MinMax' */ if (rty_cnt_0 < rtu_max) { - /* Update for UnitDelay: '/UnitDelay' */ + /* Update for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = rty_cnt_0; } else { - /* Update for UnitDelay: '/UnitDelay' */ + /* Update for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = rtu_max; } - /* End of MinMax: '/MinMax' */ + /* End of MinMax: '/MinMax' */ return rty_cnt_0; } -/* System initialize for atomic system: '/PI_clamp_fixdt' */ -void PI_clamp_fixdt_Init(DW_PI_clamp_fixdt *localDW) -{ - /* InitializeConditions for Delay: '/Resettable Delay' */ - localDW->icLoad = 1U; -} - -/* Output and update for atomic system: '/PI_clamp_fixdt' */ -void PI_clamp_fixdt(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, int32_T - rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T - rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt - *localDW) -{ - boolean_T rtb_LowerRelop1_c; - boolean_T rtb_UpperRelop_e; - int32_T rtb_Sum1_n; - int32_T q0; - int32_T tmp; - int16_T tmp_0; - - /* Sum: '/Sum2' incorporates: - * Product: '/Divide2' - */ - q0 = rtu_err * rtu_I; - if ((q0 < 0) && (rtu_ext_limProt < MIN_int32_T - q0)) { - q0 = MIN_int32_T; - } else if ((q0 > 0) && (rtu_ext_limProt > MAX_int32_T - q0)) { - q0 = MAX_int32_T; - } else { - q0 += rtu_ext_limProt; - } - - /* Delay: '/Resettable Delay' */ - if (localDW->icLoad != 0) { - localDW->ResettableDelay_DSTATE = rtu_init; - } - - /* Switch: '/Switch1' incorporates: - * Constant: '/Constant' - * Sum: '/Sum2' - * UnitDelay: '/UnitDelay1' - */ - if (localDW->UnitDelay1_DSTATE) { - tmp = 0; - } else { - tmp = q0; - } - - /* End of Switch: '/Switch1' */ - - /* Sum: '/Sum1' incorporates: - * Delay: '/Resettable Delay' - */ - rtb_Sum1_n = tmp + localDW->ResettableDelay_DSTATE; - - /* Product: '/Divide5' */ - tmp = (rtu_err * rtu_P) >> 11; - if (tmp > 32767) { - tmp = 32767; - } else { - if (tmp < -32768) { - tmp = -32768; - } - } - - /* Sum: '/Sum1' incorporates: - * DataTypeConversion: '/Data Type Conversion1' - * Product: '/Divide5' - */ - tmp = (((rtb_Sum1_n >> 16) << 1) + tmp) >> 1; - if (tmp > 32767) { - tmp = 32767; - } else { - if (tmp < -32768) { - tmp = -32768; - } - } - - /* RelationalOperator: '/LowerRelop1' incorporates: - * Sum: '/Sum1' - */ - rtb_LowerRelop1_c = ((int16_T)tmp > rtu_satMax); - - /* RelationalOperator: '/UpperRelop' incorporates: - * Sum: '/Sum1' - */ - rtb_UpperRelop_e = ((int16_T)tmp < rtu_satMin); - - /* Switch: '/Switch1' incorporates: - * Sum: '/Sum1' - * Switch: '/Switch3' - */ - if (rtb_LowerRelop1_c) { - *rty_out = rtu_satMax; - } else if (rtb_UpperRelop_e) { - /* Switch: '/Switch3' */ - *rty_out = rtu_satMin; - } else { - *rty_out = (int16_T)tmp; - } - - /* End of Switch: '/Switch1' */ - - /* Signum: '/SignDeltaU2' incorporates: - * Sum: '/Sum2' - */ - if (q0 < 0) { - q0 = -1; - } else { - q0 = (q0 > 0); - } - - /* End of Signum: '/SignDeltaU2' */ - - /* Signum: '/SignDeltaU3' incorporates: - * Sum: '/Sum1' - */ - if ((int16_T)tmp < 0) { - tmp_0 = -1; - } else { - tmp_0 = (int16_T)((int16_T)tmp > 0); - } - - /* End of Signum: '/SignDeltaU3' */ - - /* Update for UnitDelay: '/UnitDelay1' incorporates: - * DataTypeConversion: '/DataTypeConv4' - * Logic: '/AND1' - * Logic: '/AND1' - * RelationalOperator: '/Equal1' - */ - localDW->UnitDelay1_DSTATE = ((q0 == tmp_0) && (rtb_LowerRelop1_c || - rtb_UpperRelop_e)); - - /* Update for Delay: '/Resettable Delay' */ - localDW->icLoad = 0U; - localDW->ResettableDelay_DSTATE = rtb_Sum1_n; -} - -/* System initialize for atomic system: '/PI_clamp_fixdt' */ -void PI_clamp_fixdt_g_Init(DW_PI_clamp_fixdt_i *localDW) -{ - /* InitializeConditions for Delay: '/Resettable Delay' */ - localDW->icLoad = 1U; -} - -/* System reset for atomic system: '/PI_clamp_fixdt' */ -void PI_clamp_fixdt_g_Reset(DW_PI_clamp_fixdt_i *localDW) -{ - /* InitializeConditions for UnitDelay: '/UnitDelay1' */ - localDW->UnitDelay1_DSTATE = false; - - /* InitializeConditions for Delay: '/Resettable Delay' */ - localDW->icLoad = 1U; -} - -/* Output and update for atomic system: '/PI_clamp_fixdt' */ -int16_T PI_clamp_fixdt_o(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, - int16_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T - rtu_ext_limProt, DW_PI_clamp_fixdt_i *localDW) -{ - boolean_T rtb_LowerRelop1_l; - boolean_T rtb_UpperRelop_f2; - int32_T rtb_Sum1_o; - int32_T q0; - int32_T tmp; - int16_T tmp_0; - int16_T rty_out_0; - - /* Sum: '/Sum2' incorporates: - * Product: '/Divide2' - */ - q0 = rtu_err * rtu_I; - if ((q0 < 0) && (rtu_ext_limProt < MIN_int32_T - q0)) { - q0 = MIN_int32_T; - } else if ((q0 > 0) && (rtu_ext_limProt > MAX_int32_T - q0)) { - q0 = MAX_int32_T; - } else { - q0 += rtu_ext_limProt; - } - - /* Delay: '/Resettable Delay' */ - if (localDW->icLoad != 0) { - localDW->ResettableDelay_DSTATE = rtu_init << 16; - } - - /* Switch: '/Switch1' incorporates: - * Constant: '/Constant' - * Sum: '/Sum2' - * UnitDelay: '/UnitDelay1' - */ - if (localDW->UnitDelay1_DSTATE) { - tmp = 0; - } else { - tmp = q0; - } - - /* End of Switch: '/Switch1' */ - - /* Sum: '/Sum1' incorporates: - * Delay: '/Resettable Delay' - */ - rtb_Sum1_o = tmp + localDW->ResettableDelay_DSTATE; - - /* Product: '/Divide5' */ - tmp = (rtu_err * rtu_P) >> 11; - if (tmp > 32767) { - tmp = 32767; - } else { - if (tmp < -32768) { - tmp = -32768; - } - } - - /* Sum: '/Sum1' incorporates: - * DataTypeConversion: '/Data Type Conversion1' - * Product: '/Divide5' - */ - tmp = (((rtb_Sum1_o >> 16) << 1) + tmp) >> 1; - if (tmp > 32767) { - tmp = 32767; - } else { - if (tmp < -32768) { - tmp = -32768; - } - } - - /* RelationalOperator: '/LowerRelop1' incorporates: - * Sum: '/Sum1' - */ - rtb_LowerRelop1_l = ((int16_T)tmp > rtu_satMax); - - /* RelationalOperator: '/UpperRelop' incorporates: - * Sum: '/Sum1' - */ - rtb_UpperRelop_f2 = ((int16_T)tmp < rtu_satMin); - - /* Switch: '/Switch1' incorporates: - * Sum: '/Sum1' - * Switch: '/Switch3' - */ - if (rtb_LowerRelop1_l) { - rty_out_0 = rtu_satMax; - } else if (rtb_UpperRelop_f2) { - /* Switch: '/Switch3' */ - rty_out_0 = rtu_satMin; - } else { - rty_out_0 = (int16_T)tmp; - } - - /* End of Switch: '/Switch1' */ - - /* Signum: '/SignDeltaU2' incorporates: - * Sum: '/Sum2' - */ - if (q0 < 0) { - q0 = -1; - } else { - q0 = (q0 > 0); - } - - /* End of Signum: '/SignDeltaU2' */ - - /* Signum: '/SignDeltaU3' incorporates: - * Sum: '/Sum1' - */ - if ((int16_T)tmp < 0) { - tmp_0 = -1; - } else { - tmp_0 = (int16_T)((int16_T)tmp > 0); - } - - /* End of Signum: '/SignDeltaU3' */ - - /* Update for UnitDelay: '/UnitDelay1' incorporates: - * DataTypeConversion: '/DataTypeConv4' - * Logic: '/AND1' - * Logic: '/AND1' - * RelationalOperator: '/Equal1' - */ - localDW->UnitDelay1_DSTATE = ((q0 == tmp_0) && (rtb_LowerRelop1_l || - rtb_UpperRelop_f2)); - - /* Update for Delay: '/Resettable Delay' */ - localDW->icLoad = 0U; - localDW->ResettableDelay_DSTATE = rtb_Sum1_o; - return rty_out_0; -} - -/* System initialize for atomic system: '/PI_clamp_fixdt' */ -void PI_clamp_fixdt_k_Init(DW_PI_clamp_fixdt_e *localDW) -{ - /* InitializeConditions for Delay: '/Resettable Delay' */ - localDW->icLoad = 1U; -} - -/* System reset for atomic system: '/PI_clamp_fixdt' */ -void PI_clamp_fixdt_b_Reset(DW_PI_clamp_fixdt_e *localDW) -{ - /* InitializeConditions for UnitDelay: '/UnitDelay1' */ - localDW->UnitDelay1_DSTATE = false; - - /* InitializeConditions for Delay: '/Resettable Delay' */ - localDW->icLoad = 1U; -} - -/* Output and update for atomic system: '/PI_clamp_fixdt' */ -int16_T PI_clamp_fixdt_a(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, - int16_T rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T - rtu_ext_limProt, DW_PI_clamp_fixdt_e *localDW) -{ - boolean_T rtb_LowerRelop1_lt; - boolean_T rtb_UpperRelop_i; - int16_T rtb_Sum1_n; - int16_T tmp; - int32_T tmp_0; - int32_T q0; - int16_T rty_out_0; - - /* Sum: '/Sum2' incorporates: - * Product: '/Divide2' - */ - q0 = rtu_err * rtu_I; - if ((q0 < 0) && (rtu_ext_limProt < MIN_int32_T - q0)) { - q0 = MIN_int32_T; - } else if ((q0 > 0) && (rtu_ext_limProt > MAX_int32_T - q0)) { - q0 = MAX_int32_T; - } else { - q0 += rtu_ext_limProt; - } - - /* Delay: '/Resettable Delay' */ - if (localDW->icLoad != 0) { - localDW->ResettableDelay_DSTATE = rtu_init; - } - - /* Switch: '/Switch1' incorporates: - * Constant: '/Constant' - * Sum: '/Sum2' - * UnitDelay: '/UnitDelay1' - */ - if (localDW->UnitDelay1_DSTATE) { - tmp = 0; - } else { - tmp = (int16_T)(((q0 < 0 ? 65535 : 0) + q0) >> 16); - } - - /* End of Switch: '/Switch1' */ - - /* Sum: '/Sum1' incorporates: - * Delay: '/Resettable Delay' - */ - rtb_Sum1_n = (int16_T)(tmp + localDW->ResettableDelay_DSTATE); - - /* Product: '/Divide5' */ - tmp_0 = (rtu_err * rtu_P) >> 11; - if (tmp_0 > 32767) { - tmp_0 = 32767; - } else { - if (tmp_0 < -32768) { - tmp_0 = -32768; - } - } - - /* Sum: '/Sum1' incorporates: - * Product: '/Divide5' - */ - tmp_0 = ((rtb_Sum1_n << 1) + tmp_0) >> 1; - if (tmp_0 > 32767) { - tmp_0 = 32767; - } else { - if (tmp_0 < -32768) { - tmp_0 = -32768; - } - } - - /* RelationalOperator: '/LowerRelop1' incorporates: - * Sum: '/Sum1' - */ - rtb_LowerRelop1_lt = ((int16_T)tmp_0 > rtu_satMax); - - /* RelationalOperator: '/UpperRelop' incorporates: - * Sum: '/Sum1' - */ - rtb_UpperRelop_i = ((int16_T)tmp_0 < rtu_satMin); - - /* Switch: '/Switch1' incorporates: - * Sum: '/Sum1' - * Switch: '/Switch3' - */ - if (rtb_LowerRelop1_lt) { - rty_out_0 = rtu_satMax; - } else if (rtb_UpperRelop_i) { - /* Switch: '/Switch3' */ - rty_out_0 = rtu_satMin; - } else { - rty_out_0 = (int16_T)tmp_0; - } - - /* End of Switch: '/Switch1' */ - - /* Signum: '/SignDeltaU2' incorporates: - * Sum: '/Sum2' - */ - if (q0 < 0) { - q0 = -1; - } else { - q0 = (q0 > 0); - } - - /* End of Signum: '/SignDeltaU2' */ - - /* Signum: '/SignDeltaU3' incorporates: - * Sum: '/Sum1' - */ - if ((int16_T)tmp_0 < 0) { - tmp = -1; - } else { - tmp = (int16_T)((int16_T)tmp_0 > 0); - } - - /* End of Signum: '/SignDeltaU3' */ - - /* Update for UnitDelay: '/UnitDelay1' incorporates: - * DataTypeConversion: '/DataTypeConv4' - * Logic: '/AND1' - * Logic: '/AND1' - * RelationalOperator: '/Equal1' - */ - localDW->UnitDelay1_DSTATE = ((q0 == tmp) && (rtb_LowerRelop1_lt || - rtb_UpperRelop_i)); - - /* Update for Delay: '/Resettable Delay' */ - localDW->icLoad = 0U; - localDW->ResettableDelay_DSTATE = rtb_Sum1_n; - return rty_out_0; -} - -/* System reset for atomic system: '/Low_Pass_Filter' */ +/* System reset for atomic system: '/Low_Pass_Filter' */ void Low_Pass_Filter_Reset(DW_Low_Pass_Filter *localDW) { - /* InitializeConditions for UnitDelay: '/UnitDelay1' */ + /* InitializeConditions for UnitDelay: '/UnitDelay1' */ localDW->UnitDelay1_DSTATE[0] = 0; localDW->UnitDelay1_DSTATE[1] = 0; } -/* Output and update for atomic system: '/Low_Pass_Filter' */ +/* Output and update for atomic system: '/Low_Pass_Filter' */ void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T rty_y[2], DW_Low_Pass_Filter *localDW) { int32_T rtb_Sum3_g; - /* Sum: '/Sum2' incorporates: - * UnitDelay: '/UnitDelay1' + /* Sum: '/Sum2' incorporates: + * UnitDelay: '/UnitDelay1' */ rtb_Sum3_g = rtu_u[0] - (localDW->UnitDelay1_DSTATE[0] >> 16); if (rtb_Sum3_g > 32767) { @@ -696,21 +262,21 @@ void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T rty_y[2] } } - /* Sum: '/Sum3' incorporates: - * Product: '/Divide3' - * Sum: '/Sum2' - * UnitDelay: '/UnitDelay1' + /* Sum: '/Sum3' incorporates: + * Product: '/Divide3' + * Sum: '/Sum2' + * UnitDelay: '/UnitDelay1' */ rtb_Sum3_g = rtu_coef * rtb_Sum3_g + localDW->UnitDelay1_DSTATE[0]; - /* DataTypeConversion: '/Data Type Conversion' */ + /* DataTypeConversion: '/Data Type Conversion' */ rty_y[0] = (int16_T)(rtb_Sum3_g >> 16); - /* Update for UnitDelay: '/UnitDelay1' */ + /* Update for UnitDelay: '/UnitDelay1' */ localDW->UnitDelay1_DSTATE[0] = rtb_Sum3_g; - /* Sum: '/Sum2' incorporates: - * UnitDelay: '/UnitDelay1' + /* Sum: '/Sum2' incorporates: + * UnitDelay: '/UnitDelay1' */ rtb_Sum3_g = rtu_u[1] - (localDW->UnitDelay1_DSTATE[1] >> 16); if (rtb_Sum3_g > 32767) { @@ -721,122 +287,44 @@ void Low_Pass_Filter(const int16_T rtu_u[2], uint16_T rtu_coef, int16_T rty_y[2] } } - /* Sum: '/Sum3' incorporates: - * Product: '/Divide3' - * Sum: '/Sum2' - * UnitDelay: '/UnitDelay1' + /* Sum: '/Sum3' incorporates: + * Product: '/Divide3' + * Sum: '/Sum2' + * UnitDelay: '/UnitDelay1' */ rtb_Sum3_g = rtu_coef * rtb_Sum3_g + localDW->UnitDelay1_DSTATE[1]; - /* DataTypeConversion: '/Data Type Conversion' */ + /* DataTypeConversion: '/Data Type Conversion' */ rty_y[1] = (int16_T)(rtb_Sum3_g >> 16); - /* Update for UnitDelay: '/UnitDelay1' */ + /* Update for UnitDelay: '/UnitDelay1' */ localDW->UnitDelay1_DSTATE[1] = rtb_Sum3_g; } /* * System initialize for atomic system: - * '/I_backCalc_fixdt' - * '/I_backCalc_fixdt1' - * '/I_backCalc_fixdt' + * '/Counter' + * '/Counter' */ -void I_backCalc_fixdt_Init(DW_I_backCalc_fixdt *localDW, int32_T rtp_yInit) +void Counter_b_Init(DW_Counter_b *localDW, uint16_T rtp_z_cntInit) { - /* InitializeConditions for UnitDelay: '/UnitDelay' */ - localDW->UnitDelay_DSTATE_h = rtp_yInit; -} - -/* - * Output and update for atomic system: - * '/I_backCalc_fixdt' - * '/I_backCalc_fixdt1' - * '/I_backCalc_fixdt' - */ -void I_backCalc_fixdt(int16_T rtu_err, uint16_T rtu_I, uint16_T rtu_Kb, int16_T - rtu_satMax, int16_T rtu_satMin, int16_T *rty_out, - DW_I_backCalc_fixdt *localDW) -{ - int32_T rtb_Sum1_m; - int16_T rtb_DataTypeConversion1_no; - - /* Sum: '/Sum2' incorporates: - * Product: '/Divide2' - * UnitDelay: '/UnitDelay' - */ - rtb_Sum1_m = (rtu_err * rtu_I) >> 4; - if ((rtb_Sum1_m < 0) && (localDW->UnitDelay_DSTATE < MIN_int32_T - rtb_Sum1_m)) - { - rtb_Sum1_m = MIN_int32_T; - } else if ((rtb_Sum1_m > 0) && (localDW->UnitDelay_DSTATE > MAX_int32_T - - rtb_Sum1_m)) { - rtb_Sum1_m = MAX_int32_T; - } else { - rtb_Sum1_m += localDW->UnitDelay_DSTATE; - } - - /* End of Sum: '/Sum2' */ - - /* Sum: '/Sum1' incorporates: - * UnitDelay: '/UnitDelay' - */ - rtb_Sum1_m += localDW->UnitDelay_DSTATE_h; - - /* DataTypeConversion: '/Data Type Conversion1' */ - rtb_DataTypeConversion1_no = (int16_T)(rtb_Sum1_m >> 12); - - /* Switch: '/Switch2' incorporates: - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' - * Switch: '/Switch' - */ - if (rtb_DataTypeConversion1_no > rtu_satMax) { - *rty_out = rtu_satMax; - } else if (rtb_DataTypeConversion1_no < rtu_satMin) { - /* Switch: '/Switch' */ - *rty_out = rtu_satMin; - } else { - *rty_out = rtb_DataTypeConversion1_no; - } - - /* End of Switch: '/Switch2' */ - - /* Update for UnitDelay: '/UnitDelay' incorporates: - * Product: '/Divide1' - * Sum: '/Sum3' - */ - localDW->UnitDelay_DSTATE = (int16_T)(*rty_out - rtb_DataTypeConversion1_no) * - rtu_Kb; - - /* Update for UnitDelay: '/UnitDelay' */ - localDW->UnitDelay_DSTATE_h = rtb_Sum1_m; -} - -/* - * System initialize for atomic system: - * '/Counter' - * '/Counter' - */ -void Counter_b_Init(DW_Counter_l *localDW, uint16_T rtp_z_cntInit) -{ - /* InitializeConditions for UnitDelay: '/UnitDelay' */ + /* InitializeConditions for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = rtp_z_cntInit; } /* * Output and update for atomic system: - * '/Counter' - * '/Counter' + * '/Counter' + * '/Counter' */ -uint16_T Counter_i(uint16_T rtu_inc, uint16_T rtu_max, boolean_T rtu_rst, - DW_Counter_l *localDW) +void Counter_n(uint16_T rtu_inc, uint16_T rtu_max, boolean_T rtu_rst, uint16_T + *rty_cnt, DW_Counter_b *localDW) { uint16_T rtu_rst_0; - uint16_T rty_cnt_0; - /* Switch: '/Switch1' incorporates: - * Constant: '/Constant23' - * UnitDelay: '/UnitDelay' + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant23' + * UnitDelay: '/UnitDelay' */ if (rtu_rst) { rtu_rst_0 = 0U; @@ -844,141 +332,672 @@ uint16_T Counter_i(uint16_T rtu_inc, uint16_T rtu_max, boolean_T rtu_rst, rtu_rst_0 = localDW->UnitDelay_DSTATE; } - /* End of Switch: '/Switch1' */ + /* End of Switch: '/Switch1' */ - /* Sum: '/Sum1' */ - rty_cnt_0 = (uint16_T)((uint32_T)rtu_inc + rtu_rst_0); + /* Sum: '/Sum1' */ + *rty_cnt = (uint16_T)((uint32_T)rtu_inc + rtu_rst_0); - /* MinMax: '/MinMax' */ - if (rty_cnt_0 < rtu_max) { - /* Update for UnitDelay: '/UnitDelay' */ - localDW->UnitDelay_DSTATE = rty_cnt_0; + /* MinMax: '/MinMax' */ + if (*rty_cnt < rtu_max) { + /* Update for UnitDelay: '/UnitDelay' */ + localDW->UnitDelay_DSTATE = *rty_cnt; } else { - /* Update for UnitDelay: '/UnitDelay' */ + /* Update for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = rtu_max; } - /* End of MinMax: '/MinMax' */ - return rty_cnt_0; + /* End of MinMax: '/MinMax' */ } /* * Output and update for atomic system: - * '/either_edge' - * '/either_edge' + * '/either_edge' + * '/either_edge' */ -boolean_T either_edge(boolean_T rtu_u, DW_either_edge *localDW) +void either_edge(boolean_T rtu_u, boolean_T *rty_y, DW_either_edge *localDW) { - boolean_T rty_y_0; - - /* RelationalOperator: '/Relational Operator' incorporates: - * UnitDelay: '/UnitDelay' + /* RelationalOperator: '/Relational Operator' incorporates: + * UnitDelay: '/UnitDelay' */ - rty_y_0 = (rtu_u != localDW->UnitDelay_DSTATE); + *rty_y = (rtu_u != localDW->UnitDelay_DSTATE); - /* Update for UnitDelay: '/UnitDelay' */ + /* Update for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = rtu_u; - return rty_y_0; } -/* System initialize for atomic system: '/Debounce_Filter' */ +/* System initialize for atomic system: '/Debounce_Filter' */ void Debounce_Filter_Init(DW_Debounce_Filter *localDW) { - /* SystemInitialize for IfAction SubSystem: '/Qualification' */ + /* SystemInitialize for IfAction SubSystem: '/Qualification' */ - /* SystemInitialize for Atomic SubSystem: '/Counter' */ - Counter_b_Init(&localDW->Counter_i0, 0U); + /* SystemInitialize for Atomic SubSystem: '/Counter' */ + Counter_b_Init(&localDW->Counter_n1, 0U); - /* End of SystemInitialize for SubSystem: '/Counter' */ + /* End of SystemInitialize for SubSystem: '/Counter' */ - /* End of SystemInitialize for SubSystem: '/Qualification' */ + /* End of SystemInitialize for SubSystem: '/Qualification' */ - /* SystemInitialize for IfAction SubSystem: '/Dequalification' */ + /* SystemInitialize for IfAction SubSystem: '/Dequalification' */ - /* SystemInitialize for Atomic SubSystem: '/Counter' */ - Counter_b_Init(&localDW->Counter_h, 0U); + /* SystemInitialize for Atomic SubSystem: '/Counter' */ + Counter_b_Init(&localDW->Counter_e, 0U); - /* End of SystemInitialize for SubSystem: '/Counter' */ + /* End of SystemInitialize for SubSystem: '/Counter' */ - /* End of SystemInitialize for SubSystem: '/Dequalification' */ + /* End of SystemInitialize for SubSystem: '/Dequalification' */ } -/* Output and update for atomic system: '/Debounce_Filter' */ +/* Output and update for atomic system: '/Debounce_Filter' */ void Debounce_Filter(boolean_T rtu_u, uint16_T rtu_tAcv, uint16_T rtu_tDeacv, boolean_T *rty_y, DW_Debounce_Filter *localDW) { - boolean_T rtb_UnitDelay_o; - uint16_T rtb_Sum1_l; - boolean_T rtb_RelationalOperator_f; + uint16_T rtb_Sum1_n; + boolean_T rtb_RelationalOperator_g; - /* UnitDelay: '/UnitDelay' */ - rtb_UnitDelay_o = localDW->UnitDelay_DSTATE; + /* Outputs for Atomic SubSystem: '/either_edge' */ + either_edge(rtu_u, &rtb_RelationalOperator_g, &localDW->either_edge_p); - /* Outputs for Atomic SubSystem: '/either_edge' */ - rtb_RelationalOperator_f = either_edge(rtu_u, &localDW->either_edge_k); + /* End of Outputs for SubSystem: '/either_edge' */ - /* End of Outputs for SubSystem: '/either_edge' */ - - /* If: '/If2' incorporates: - * Constant: '/Constant6' - * Constant: '/Constant6' - * Inport: '/yPrev' - * Logic: '/Logical Operator1' - * Logic: '/Logical Operator2' - * Logic: '/Logical Operator3' - * Logic: '/Logical Operator4' + /* If: '/If2' incorporates: + * Constant: '/Constant6' + * Constant: '/Constant6' + * Inport: '/yPrev' + * Logic: '/Logical Operator1' + * Logic: '/Logical Operator2' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/UnitDelay' */ - if (rtu_u && (!rtb_UnitDelay_o)) { - /* Outputs for IfAction SubSystem: '/Qualification' incorporates: + if (rtu_u && (!localDW->UnitDelay_DSTATE)) { + /* Outputs for IfAction SubSystem: '/Qualification' incorporates: + * ActionPort: '/Action Port' + */ + + /* Outputs for Atomic SubSystem: '/Counter' */ + Counter_n(1U, rtu_tAcv, rtb_RelationalOperator_g, &rtb_Sum1_n, + &localDW->Counter_n1); + + /* End of Outputs for SubSystem: '/Counter' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant6' + * RelationalOperator: '/Relational Operator2' + */ + *rty_y = ((rtb_Sum1_n > rtu_tAcv) || localDW->UnitDelay_DSTATE); + + /* End of Outputs for SubSystem: '/Qualification' */ + } else if ((!rtu_u) && localDW->UnitDelay_DSTATE) { + /* Outputs for IfAction SubSystem: '/Dequalification' incorporates: + * ActionPort: '/Action Port' + */ + + /* Outputs for Atomic SubSystem: '/Counter' */ + Counter_n(1U, rtu_tDeacv, rtb_RelationalOperator_g, &rtb_Sum1_n, + &localDW->Counter_e); + + /* End of Outputs for SubSystem: '/Counter' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant6' + * RelationalOperator: '/Relational Operator2' + */ + *rty_y = ((!(rtb_Sum1_n > rtu_tDeacv)) && localDW->UnitDelay_DSTATE); + + /* End of Outputs for SubSystem: '/Dequalification' */ + } else { + /* Outputs for IfAction SubSystem: '/Default' incorporates: * ActionPort: '/Action Port' */ + *rty_y = localDW->UnitDelay_DSTATE; - /* Outputs for Atomic SubSystem: '/Counter' */ - rtb_Sum1_l = (uint16_T) Counter_i(1U, rtu_tAcv, rtb_RelationalOperator_f, - &localDW->Counter_i0); - - /* End of Outputs for SubSystem: '/Counter' */ - - /* Switch: '/Switch2' incorporates: - * Constant: '/Constant6' - * RelationalOperator: '/Relational Operator2' - */ - *rty_y = (rtb_Sum1_l > rtu_tAcv); - - /* End of Outputs for SubSystem: '/Qualification' */ - } else if ((!rtu_u) && rtb_UnitDelay_o) { - /* Outputs for IfAction SubSystem: '/Dequalification' incorporates: - * ActionPort: '/Action Port' - */ - - /* Outputs for Atomic SubSystem: '/Counter' */ - rtb_Sum1_l = (uint16_T) Counter_i(1U, rtu_tDeacv, rtb_RelationalOperator_f, - &localDW->Counter_h); - - /* End of Outputs for SubSystem: '/Counter' */ - - /* Switch: '/Switch2' incorporates: - * Constant: '/Constant6' - * RelationalOperator: '/Relational Operator2' - */ - *rty_y = !(rtb_Sum1_l > rtu_tDeacv); - - /* End of Outputs for SubSystem: '/Dequalification' */ - } else { - /* Outputs for IfAction SubSystem: '/Default' incorporates: - * ActionPort: '/Action Port' - */ - *rty_y = rtb_UnitDelay_o; - - /* End of Outputs for SubSystem: '/Default' */ + /* End of Outputs for SubSystem: '/Default' */ } - /* End of If: '/If2' */ + /* End of If: '/If2' */ - /* Update for UnitDelay: '/UnitDelay' */ + /* Update for UnitDelay: '/UnitDelay' */ localDW->UnitDelay_DSTATE = *rty_y; } +/* + * System initialize for atomic system: + * '/I_backCalc_fixdt' + * '/I_backCalc_fixdt1' + * '/I_backCalc_fixdt' + */ +void I_backCalc_fixdt_Init(DW_I_backCalc_fixdt *localDW, int32_T rtp_yInit) +{ + /* InitializeConditions for UnitDelay: '/UnitDelay' */ + localDW->UnitDelay_DSTATE_m = rtp_yInit; +} + +/* + * System reset for atomic system: + * '/I_backCalc_fixdt' + * '/I_backCalc_fixdt1' + * '/I_backCalc_fixdt' + */ +void I_backCalc_fixdt_Reset(DW_I_backCalc_fixdt *localDW, int32_T rtp_yInit) +{ + /* InitializeConditions for UnitDelay: '/UnitDelay' */ + localDW->UnitDelay_DSTATE = 0; + + /* InitializeConditions for UnitDelay: '/UnitDelay' */ + localDW->UnitDelay_DSTATE_m = rtp_yInit; +} + +/* + * Output and update for atomic system: + * '/I_backCalc_fixdt' + * '/I_backCalc_fixdt1' + * '/I_backCalc_fixdt' + */ +void I_backCalc_fixdt(int16_T rtu_err, uint16_T rtu_I, uint16_T rtu_Kb, int16_T + rtu_satMax, int16_T rtu_satMin, int16_T *rty_out, + DW_I_backCalc_fixdt *localDW) +{ + int32_T rtb_Sum1_o; + int16_T rtb_DataTypeConversion1_gf; + + /* Sum: '/Sum2' incorporates: + * Product: '/Divide2' + * UnitDelay: '/UnitDelay' + */ + rtb_Sum1_o = (rtu_err * rtu_I) >> 4; + if ((rtb_Sum1_o < 0) && (localDW->UnitDelay_DSTATE < MIN_int32_T - rtb_Sum1_o)) + { + rtb_Sum1_o = MIN_int32_T; + } else if ((rtb_Sum1_o > 0) && (localDW->UnitDelay_DSTATE > MAX_int32_T + - rtb_Sum1_o)) { + rtb_Sum1_o = MAX_int32_T; + } else { + rtb_Sum1_o += localDW->UnitDelay_DSTATE; + } + + /* End of Sum: '/Sum2' */ + + /* Sum: '/Sum1' incorporates: + * UnitDelay: '/UnitDelay' + */ + rtb_Sum1_o += localDW->UnitDelay_DSTATE_m; + + /* DataTypeConversion: '/Data Type Conversion1' */ + rtb_DataTypeConversion1_gf = (int16_T)(rtb_Sum1_o >> 12); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_DataTypeConversion1_gf > rtu_satMax) { + *rty_out = rtu_satMax; + } else if (rtb_DataTypeConversion1_gf < rtu_satMin) { + /* Switch: '/Switch' */ + *rty_out = rtu_satMin; + } else { + *rty_out = rtb_DataTypeConversion1_gf; + } + + /* End of Switch: '/Switch2' */ + + /* Update for UnitDelay: '/UnitDelay' incorporates: + * Product: '/Divide1' + * Sum: '/Sum3' + */ + localDW->UnitDelay_DSTATE = (int16_T)(*rty_out - rtb_DataTypeConversion1_gf) * + rtu_Kb; + + /* Update for UnitDelay: '/UnitDelay' */ + localDW->UnitDelay_DSTATE_m = rtb_Sum1_o; +} + +/* System initialize for atomic system: '/PI_clamp_fixdt' */ +void PI_clamp_fixdt_Init(DW_PI_clamp_fixdt *localDW) +{ + /* InitializeConditions for Delay: '/Resettable Delay' */ + localDW->icLoad = 1U; +} + +/* System reset for atomic system: '/PI_clamp_fixdt' */ +void PI_clamp_fixdt_Reset(DW_PI_clamp_fixdt *localDW) +{ + /* InitializeConditions for UnitDelay: '/UnitDelay1' */ + localDW->UnitDelay1_DSTATE = false; + + /* InitializeConditions for Delay: '/Resettable Delay' */ + localDW->icLoad = 1U; +} + +/* Output and update for atomic system: '/PI_clamp_fixdt' */ +void PI_clamp_fixdt(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, int32_T + rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T + rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt + *localDW) +{ + boolean_T rtb_LowerRelop1_c0; + boolean_T rtb_UpperRelop_f; + int32_T rtb_Sum1_p0; + int32_T q0; + int32_T tmp; + int16_T tmp_0; + + /* Sum: '/Sum2' incorporates: + * Product: '/Divide2' + */ + q0 = rtu_err * rtu_I; + if ((q0 < 0) && (rtu_ext_limProt < MIN_int32_T - q0)) { + q0 = MIN_int32_T; + } else if ((q0 > 0) && (rtu_ext_limProt > MAX_int32_T - q0)) { + q0 = MAX_int32_T; + } else { + q0 += rtu_ext_limProt; + } + + /* Delay: '/Resettable Delay' */ + if (localDW->icLoad != 0) { + localDW->ResettableDelay_DSTATE = rtu_init; + } + + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant' + * Sum: '/Sum2' + * UnitDelay: '/UnitDelay1' + */ + if (localDW->UnitDelay1_DSTATE) { + tmp = 0; + } else { + tmp = q0; + } + + /* End of Switch: '/Switch1' */ + + /* Sum: '/Sum1' incorporates: + * Delay: '/Resettable Delay' + */ + rtb_Sum1_p0 = tmp + localDW->ResettableDelay_DSTATE; + + /* Product: '/Divide5' */ + tmp = (rtu_err * rtu_P) >> 11; + if (tmp > 32767) { + tmp = 32767; + } else { + if (tmp < -32768) { + tmp = -32768; + } + } + + /* Sum: '/Sum1' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + * Product: '/Divide5' + */ + tmp = (((rtb_Sum1_p0 >> 16) << 1) + tmp) >> 1; + if (tmp > 32767) { + tmp = 32767; + } else { + if (tmp < -32768) { + tmp = -32768; + } + } + + /* RelationalOperator: '/LowerRelop1' incorporates: + * Sum: '/Sum1' + */ + rtb_LowerRelop1_c0 = ((int16_T)tmp > rtu_satMax); + + /* RelationalOperator: '/UpperRelop' incorporates: + * Sum: '/Sum1' + */ + rtb_UpperRelop_f = ((int16_T)tmp < rtu_satMin); + + /* Switch: '/Switch1' incorporates: + * Sum: '/Sum1' + * Switch: '/Switch3' + */ + if (rtb_LowerRelop1_c0) { + *rty_out = rtu_satMax; + } else if (rtb_UpperRelop_f) { + /* Switch: '/Switch3' */ + *rty_out = rtu_satMin; + } else { + *rty_out = (int16_T)tmp; + } + + /* End of Switch: '/Switch1' */ + + /* Signum: '/SignDeltaU2' incorporates: + * Sum: '/Sum2' + */ + if (q0 < 0) { + q0 = -1; + } else { + q0 = (q0 > 0); + } + + /* End of Signum: '/SignDeltaU2' */ + + /* Signum: '/SignDeltaU3' incorporates: + * Sum: '/Sum1' + */ + if ((int16_T)tmp < 0) { + tmp_0 = -1; + } else { + tmp_0 = (int16_T)((int16_T)tmp > 0); + } + + /* End of Signum: '/SignDeltaU3' */ + + /* Update for UnitDelay: '/UnitDelay1' incorporates: + * DataTypeConversion: '/DataTypeConv4' + * Logic: '/AND1' + * Logic: '/AND1' + * RelationalOperator: '/Equal1' + */ + localDW->UnitDelay1_DSTATE = ((q0 == tmp_0) && (rtb_LowerRelop1_c0 || + rtb_UpperRelop_f)); + + /* Update for Delay: '/Resettable Delay' */ + localDW->icLoad = 0U; + localDW->ResettableDelay_DSTATE = rtb_Sum1_p0; +} + +/* System initialize for atomic system: '/PI_clamp_fixdt' */ +void PI_clamp_fixdt_d_Init(DW_PI_clamp_fixdt_m *localDW) +{ + /* InitializeConditions for Delay: '/Resettable Delay' */ + localDW->icLoad = 1U; +} + +/* System reset for atomic system: '/PI_clamp_fixdt' */ +void PI_clamp_fixdt_b_Reset(DW_PI_clamp_fixdt_m *localDW) +{ + /* InitializeConditions for UnitDelay: '/UnitDelay1' */ + localDW->UnitDelay1_DSTATE = false; + + /* InitializeConditions for Delay: '/Resettable Delay' */ + localDW->icLoad = 1U; +} + +/* Output and update for atomic system: '/PI_clamp_fixdt' */ +void PI_clamp_fixdt_l(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, int16_T + rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T + rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt_m + *localDW) +{ + boolean_T rtb_LowerRelop1_l; + boolean_T rtb_UpperRelop_l; + int32_T rtb_Sum1_ni; + int32_T q0; + int32_T tmp; + int16_T tmp_0; + + /* Sum: '/Sum2' incorporates: + * Product: '/Divide2' + */ + q0 = rtu_err * rtu_I; + if ((q0 < 0) && (rtu_ext_limProt < MIN_int32_T - q0)) { + q0 = MIN_int32_T; + } else if ((q0 > 0) && (rtu_ext_limProt > MAX_int32_T - q0)) { + q0 = MAX_int32_T; + } else { + q0 += rtu_ext_limProt; + } + + /* Delay: '/Resettable Delay' */ + if (localDW->icLoad != 0) { + localDW->ResettableDelay_DSTATE = rtu_init << 16; + } + + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant' + * Sum: '/Sum2' + * UnitDelay: '/UnitDelay1' + */ + if (localDW->UnitDelay1_DSTATE) { + tmp = 0; + } else { + tmp = q0; + } + + /* End of Switch: '/Switch1' */ + + /* Sum: '/Sum1' incorporates: + * Delay: '/Resettable Delay' + */ + rtb_Sum1_ni = tmp + localDW->ResettableDelay_DSTATE; + + /* Product: '/Divide5' */ + tmp = (rtu_err * rtu_P) >> 11; + if (tmp > 32767) { + tmp = 32767; + } else { + if (tmp < -32768) { + tmp = -32768; + } + } + + /* Sum: '/Sum1' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + * Product: '/Divide5' + */ + tmp = (((rtb_Sum1_ni >> 16) << 1) + tmp) >> 1; + if (tmp > 32767) { + tmp = 32767; + } else { + if (tmp < -32768) { + tmp = -32768; + } + } + + /* RelationalOperator: '/LowerRelop1' incorporates: + * Sum: '/Sum1' + */ + rtb_LowerRelop1_l = ((int16_T)tmp > rtu_satMax); + + /* RelationalOperator: '/UpperRelop' incorporates: + * Sum: '/Sum1' + */ + rtb_UpperRelop_l = ((int16_T)tmp < rtu_satMin); + + /* Switch: '/Switch1' incorporates: + * Sum: '/Sum1' + * Switch: '/Switch3' + */ + if (rtb_LowerRelop1_l) { + *rty_out = rtu_satMax; + } else if (rtb_UpperRelop_l) { + /* Switch: '/Switch3' */ + *rty_out = rtu_satMin; + } else { + *rty_out = (int16_T)tmp; + } + + /* End of Switch: '/Switch1' */ + + /* Signum: '/SignDeltaU2' incorporates: + * Sum: '/Sum2' + */ + if (q0 < 0) { + q0 = -1; + } else { + q0 = (q0 > 0); + } + + /* End of Signum: '/SignDeltaU2' */ + + /* Signum: '/SignDeltaU3' incorporates: + * Sum: '/Sum1' + */ + if ((int16_T)tmp < 0) { + tmp_0 = -1; + } else { + tmp_0 = (int16_T)((int16_T)tmp > 0); + } + + /* End of Signum: '/SignDeltaU3' */ + + /* Update for UnitDelay: '/UnitDelay1' incorporates: + * DataTypeConversion: '/DataTypeConv4' + * Logic: '/AND1' + * Logic: '/AND1' + * RelationalOperator: '/Equal1' + */ + localDW->UnitDelay1_DSTATE = ((q0 == tmp_0) && (rtb_LowerRelop1_l || + rtb_UpperRelop_l)); + + /* Update for Delay: '/Resettable Delay' */ + localDW->icLoad = 0U; + localDW->ResettableDelay_DSTATE = rtb_Sum1_ni; +} + +/* System initialize for atomic system: '/PI_clamp_fixdt' */ +void PI_clamp_fixdt_f_Init(DW_PI_clamp_fixdt_g *localDW) +{ + /* InitializeConditions for Delay: '/Resettable Delay' */ + localDW->icLoad = 1U; +} + +/* System reset for atomic system: '/PI_clamp_fixdt' */ +void PI_clamp_fixdt_g_Reset(DW_PI_clamp_fixdt_g *localDW) +{ + /* InitializeConditions for UnitDelay: '/UnitDelay1' */ + localDW->UnitDelay1_DSTATE = false; + + /* InitializeConditions for Delay: '/Resettable Delay' */ + localDW->icLoad = 1U; +} + +/* Output and update for atomic system: '/PI_clamp_fixdt' */ +void PI_clamp_fixdt_k(int16_T rtu_err, uint16_T rtu_P, uint16_T rtu_I, int16_T + rtu_init, int16_T rtu_satMax, int16_T rtu_satMin, int32_T + rtu_ext_limProt, int16_T *rty_out, DW_PI_clamp_fixdt_g + *localDW) +{ + boolean_T rtb_LowerRelop1_i3; + boolean_T rtb_UpperRelop_i; + int16_T rtb_Sum1_bm; + int16_T tmp; + int32_T tmp_0; + int32_T q0; + + /* Sum: '/Sum2' incorporates: + * Product: '/Divide2' + */ + q0 = rtu_err * rtu_I; + if ((q0 < 0) && (rtu_ext_limProt < MIN_int32_T - q0)) { + q0 = MIN_int32_T; + } else if ((q0 > 0) && (rtu_ext_limProt > MAX_int32_T - q0)) { + q0 = MAX_int32_T; + } else { + q0 += rtu_ext_limProt; + } + + /* Delay: '/Resettable Delay' */ + if (localDW->icLoad != 0) { + localDW->ResettableDelay_DSTATE = rtu_init; + } + + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant' + * Sum: '/Sum2' + * UnitDelay: '/UnitDelay1' + */ + if (localDW->UnitDelay1_DSTATE) { + tmp = 0; + } else { + tmp = (int16_T)(((q0 < 0 ? 65535 : 0) + q0) >> 16); + } + + /* End of Switch: '/Switch1' */ + + /* Sum: '/Sum1' incorporates: + * Delay: '/Resettable Delay' + */ + rtb_Sum1_bm = (int16_T)(tmp + localDW->ResettableDelay_DSTATE); + + /* Product: '/Divide5' */ + tmp_0 = (rtu_err * rtu_P) >> 11; + if (tmp_0 > 32767) { + tmp_0 = 32767; + } else { + if (tmp_0 < -32768) { + tmp_0 = -32768; + } + } + + /* Sum: '/Sum1' incorporates: + * Product: '/Divide5' + */ + tmp_0 = ((rtb_Sum1_bm << 1) + tmp_0) >> 1; + if (tmp_0 > 32767) { + tmp_0 = 32767; + } else { + if (tmp_0 < -32768) { + tmp_0 = -32768; + } + } + + /* RelationalOperator: '/LowerRelop1' incorporates: + * Sum: '/Sum1' + */ + rtb_LowerRelop1_i3 = ((int16_T)tmp_0 > rtu_satMax); + + /* RelationalOperator: '/UpperRelop' incorporates: + * Sum: '/Sum1' + */ + rtb_UpperRelop_i = ((int16_T)tmp_0 < rtu_satMin); + + /* Switch: '/Switch1' incorporates: + * Sum: '/Sum1' + * Switch: '/Switch3' + */ + if (rtb_LowerRelop1_i3) { + *rty_out = rtu_satMax; + } else if (rtb_UpperRelop_i) { + /* Switch: '/Switch3' */ + *rty_out = rtu_satMin; + } else { + *rty_out = (int16_T)tmp_0; + } + + /* End of Switch: '/Switch1' */ + + /* Signum: '/SignDeltaU2' incorporates: + * Sum: '/Sum2' + */ + if (q0 < 0) { + q0 = -1; + } else { + q0 = (q0 > 0); + } + + /* End of Signum: '/SignDeltaU2' */ + + /* Signum: '/SignDeltaU3' incorporates: + * Sum: '/Sum1' + */ + if ((int16_T)tmp_0 < 0) { + tmp = -1; + } else { + tmp = (int16_T)((int16_T)tmp_0 > 0); + } + + /* End of Signum: '/SignDeltaU3' */ + + /* Update for UnitDelay: '/UnitDelay1' incorporates: + * DataTypeConversion: '/DataTypeConv4' + * Logic: '/AND1' + * Logic: '/AND1' + * RelationalOperator: '/Equal1' + */ + localDW->UnitDelay1_DSTATE = ((q0 == tmp) && (rtb_LowerRelop1_i3 || + rtb_UpperRelop_i)); + + /* Update for Delay: '/Resettable Delay' */ + localDW->icLoad = 0U; + localDW->ResettableDelay_DSTATE = rtb_Sum1_bm; +} + /* Model step function */ void BLDC_controller_step(RT_MODEL *const rtM) { @@ -986,83 +1005,82 @@ void BLDC_controller_step(RT_MODEL *const rtM) DW *rtDW = ((DW *) rtM->dwork); ExtU *rtU = (ExtU *) rtM->inputs; ExtY *rtY = (ExtY *) rtM->outputs; - uint8_T rtb_Sum; boolean_T rtb_LogicalOperator; int8_T rtb_Sum2_h; boolean_T rtb_RelationalOperator4_d; - boolean_T rtb_RelationalOperator1_m; - uint8_T rtb_Sum_l; + boolean_T rtb_UnitDelay5_e; + uint8_T rtb_a_elecAngle_XA_g; + boolean_T rtb_LogicalOperator1_j; boolean_T rtb_LogicalOperator2_p; - boolean_T rtb_LogicalOperator4; - int16_T rtb_Switch2_k; - int16_T rtb_Abs5; - int16_T rtb_DataTypeConversion2; + boolean_T rtb_RelationalOperator1_mv; int16_T rtb_Switch1_l; int16_T rtb_Saturation; int16_T rtb_Saturation1; - int16_T rtb_Merge; - int16_T rtb_Switch2_l; - int16_T rtb_toNegative; - int32_T rtb_DataTypeConversion; + int32_T rtb_Sum1_jt; + int16_T rtb_Merge_m; + int16_T rtb_Merge1; + int16_T rtb_TmpSignalConversionAtLow_Pa[2]; int32_T rtb_Switch1; int32_T rtb_Sum1; int32_T rtb_Gain3; - int16_T rtb_TmpSignalConversionAtLow_Pa[2]; + uint8_T Sum; + int16_T Switch2; + int16_T Abs5; + int16_T DataTypeConversion2; int16_T tmp[4]; int8_T UnitDelay3; - int16_T rtb_Merge_f_idx_2; /* Outputs for Atomic SubSystem: '/BLDC_controller' */ - /* Sum: '/Sum' incorporates: - * Gain: '/g_Ha' - * Gain: '/g_Hb' + /* Sum: '/Sum' incorporates: + * Gain: '/g_Ha' + * Gain: '/g_Hb' * Inport: '/b_hallA ' * Inport: '/b_hallB' * Inport: '/b_hallC' */ - rtb_Sum = (uint8_T)((uint32_T)(uint8_T)((uint32_T)(uint8_T)(rtU->b_hallA << 2) - + (uint8_T)(rtU->b_hallB << 1)) + rtU->b_hallC); + Sum = (uint8_T)((uint32_T)(uint8_T)((uint32_T)(uint8_T)(rtU->b_hallA << 2) + + (uint8_T)(rtU->b_hallB << 1)) + rtU->b_hallC); - /* Logic: '/Logical Operator' incorporates: + /* Logic: '/Logical Operator' incorporates: * Inport: '/b_hallA ' * Inport: '/b_hallB' * Inport: '/b_hallC' - * UnitDelay: '/UnitDelay1' - * UnitDelay: '/UnitDelay2' - * UnitDelay: '/UnitDelay3' + * UnitDelay: '/UnitDelay1' + * UnitDelay: '/UnitDelay2' + * UnitDelay: '/UnitDelay3' */ rtb_LogicalOperator = (boolean_T)((rtU->b_hallA != 0) ^ (rtU->b_hallB != 0) ^ (rtU->b_hallC != 0) ^ (rtDW->UnitDelay3_DSTATE_fy != 0) ^ (rtDW->UnitDelay1_DSTATE != 0)) ^ (rtDW->UnitDelay2_DSTATE_f != 0); - /* If: '/If2' incorporates: - * If: '/If2' - * Inport: '/z_counterRawPrev' - * UnitDelay: '/UnitDelay3' + /* If: '/If2' incorporates: + * If: '/If2' + * Inport: '/z_counterRawPrev' + * UnitDelay: '/UnitDelay3' */ if (rtb_LogicalOperator) { - /* Outputs for IfAction SubSystem: '/F01_03_Direction_Detection' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/F01_03_Direction_Detection' incorporates: + * ActionPort: '/Action Port' */ - /* UnitDelay: '/UnitDelay3' */ + /* UnitDelay: '/UnitDelay3' */ UnitDelay3 = rtDW->Switch2_e; - /* Sum: '/Sum2' incorporates: - * Constant: '/vec_hallToPos' - * Selector: '/Selector' - * UnitDelay: '/UnitDelay2' + /* Sum: '/Sum2' incorporates: + * Constant: '/vec_hallToPos' + * Selector: '/Selector' + * UnitDelay: '/UnitDelay2' */ - rtb_Sum2_h = (int8_T)(rtConstP.vec_hallToPos_Value[rtb_Sum] - + rtb_Sum2_h = (int8_T)(rtConstP.vec_hallToPos_Value[Sum] - rtDW->UnitDelay2_DSTATE_b); - /* Switch: '/Switch2' incorporates: - * Constant: '/Constant20' - * Constant: '/Constant23' - * Constant: '/Constant24' - * Constant: '/Constant8' - * Logic: '/Logical Operator3' - * RelationalOperator: '/Relational Operator1' - * RelationalOperator: '/Relational Operator6' + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant20' + * Constant: '/Constant23' + * Constant: '/Constant24' + * Constant: '/Constant8' + * Logic: '/Logical Operator3' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator6' */ if ((rtb_Sum2_h == 1) || (rtb_Sum2_h == -5)) { rtDW->Switch2_e = 1; @@ -1070,38 +1088,38 @@ void BLDC_controller_step(RT_MODEL *const rtM) rtDW->Switch2_e = -1; } - /* End of Switch: '/Switch2' */ + /* End of Switch: '/Switch2' */ - /* Update for UnitDelay: '/UnitDelay2' incorporates: - * Constant: '/vec_hallToPos' - * Selector: '/Selector' + /* Update for UnitDelay: '/UnitDelay2' incorporates: + * Constant: '/vec_hallToPos' + * Selector: '/Selector' */ - rtDW->UnitDelay2_DSTATE_b = rtConstP.vec_hallToPos_Value[rtb_Sum]; + rtDW->UnitDelay2_DSTATE_b = rtConstP.vec_hallToPos_Value[Sum]; - /* End of Outputs for SubSystem: '/F01_03_Direction_Detection' */ + /* End of Outputs for SubSystem: '/F01_03_Direction_Detection' */ - /* Outputs for IfAction SubSystem: '/Raw_Motor_Speed_Estimation' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/Raw_Motor_Speed_Estimation' incorporates: + * ActionPort: '/Action Port' */ rtDW->z_counterRawPrev = rtDW->UnitDelay3_DSTATE; - /* Sum: '/Sum7' incorporates: - * Inport: '/z_counterRawPrev' - * UnitDelay: '/UnitDelay3' - * UnitDelay: '/UnitDelay4' + /* Sum: '/Sum7' incorporates: + * Inport: '/z_counterRawPrev' + * UnitDelay: '/UnitDelay3' + * UnitDelay: '/UnitDelay4' */ - rtb_Switch2_k = (int16_T)(rtDW->z_counterRawPrev - rtDW->UnitDelay4_DSTATE); + Switch2 = (int16_T)(rtDW->z_counterRawPrev - rtDW->UnitDelay4_DSTATE); - /* Abs: '/Abs2' */ - if (rtb_Switch2_k < 0) { - rtb_Switch1_l = (int16_T)-rtb_Switch2_k; + /* Abs: '/Abs2' */ + if (Switch2 < 0) { + rtb_Switch1_l = (int16_T)-Switch2; } else { - rtb_Switch1_l = rtb_Switch2_k; + rtb_Switch1_l = Switch2; } - /* End of Abs: '/Abs2' */ + /* End of Abs: '/Abs2' */ - /* Relay: '/dz_cntTrnsDet' */ + /* Relay: '/dz_cntTrnsDet' */ if (rtb_Switch1_l >= rtP->dz_cntTrnsDetHi) { rtDW->dz_cntTrnsDet_Mode = true; } else { @@ -1112,560 +1130,138 @@ void BLDC_controller_step(RT_MODEL *const rtM) rtDW->dz_cntTrnsDet = rtDW->dz_cntTrnsDet_Mode; - /* End of Relay: '/dz_cntTrnsDet' */ + /* End of Relay: '/dz_cntTrnsDet' */ - /* RelationalOperator: '/Relational Operator4' */ + /* RelationalOperator: '/Relational Operator4' */ rtb_RelationalOperator4_d = (rtDW->Switch2_e != UnitDelay3); - /* Switch: '/Switch3' incorporates: - * Constant: '/Constant4' - * Logic: '/Logical Operator1' - * Switch: '/Switch1' - * Switch: '/Switch2' - * UnitDelay: '/UnitDelay1' + /* Switch: '/Switch3' incorporates: + * Constant: '/Constant4' + * Logic: '/Logical Operator1' + * Switch: '/Switch1' + * Switch: '/Switch2' + * UnitDelay: '/UnitDelay1' */ if (rtb_RelationalOperator4_d && rtDW->UnitDelay1_DSTATE_n) { rtb_Switch1_l = 0; } else if (rtb_RelationalOperator4_d) { - /* Switch: '/Switch2' incorporates: - * UnitDelay: '/UnitDelay4' + /* Switch: '/Switch2' incorporates: + * UnitDelay: '/UnitDelay4' */ rtb_Switch1_l = rtDW->UnitDelay4_DSTATE_e; } else if (rtDW->dz_cntTrnsDet) { - /* Switch: '/Switch1' incorporates: - * Constant: '/cf_speedCoef' - * Product: '/Divide14' - * Switch: '/Switch2' + /* Switch: '/Switch1' incorporates: + * Constant: '/cf_speedCoef' + * Product: '/Divide14' + * Switch: '/Switch2' */ rtb_Switch1_l = (int16_T)((rtP->cf_speedCoef << 4) / rtDW->z_counterRawPrev); } else { - /* Switch: '/Switch1' incorporates: - * Constant: '/cf_speedCoef' - * Gain: '/g_Ha' - * Product: '/Divide13' - * Sum: '/Sum13' - * Switch: '/Switch2' - * UnitDelay: '/UnitDelay2' - * UnitDelay: '/UnitDelay3' - * UnitDelay: '/UnitDelay5' + /* Switch: '/Switch1' incorporates: + * Constant: '/cf_speedCoef' + * Gain: '/g_Ha' + * Product: '/Divide13' + * Sum: '/Sum13' + * Switch: '/Switch2' + * UnitDelay: '/UnitDelay2' + * UnitDelay: '/UnitDelay3' + * UnitDelay: '/UnitDelay5' */ rtb_Switch1_l = (int16_T)(((uint16_T)(rtP->cf_speedCoef << 2) << 4) / (int16_T)(((rtDW->UnitDelay2_DSTATE + rtDW->UnitDelay3_DSTATE_o) + rtDW->UnitDelay5_DSTATE) + rtDW->z_counterRawPrev)); } - /* End of Switch: '/Switch3' */ + /* End of Switch: '/Switch3' */ - /* Product: '/Divide11' */ + /* Product: '/Divide11' */ rtDW->Divide11 = (int16_T)(rtb_Switch1_l * rtDW->Switch2_e); - /* Update for UnitDelay: '/UnitDelay4' */ + /* Update for UnitDelay: '/UnitDelay4' */ rtDW->UnitDelay4_DSTATE = rtDW->z_counterRawPrev; - /* Update for UnitDelay: '/UnitDelay2' incorporates: - * UnitDelay: '/UnitDelay3' + /* Update for UnitDelay: '/UnitDelay2' incorporates: + * UnitDelay: '/UnitDelay3' */ rtDW->UnitDelay2_DSTATE = rtDW->UnitDelay3_DSTATE_o; - /* Update for UnitDelay: '/UnitDelay3' incorporates: - * UnitDelay: '/UnitDelay5' + /* Update for UnitDelay: '/UnitDelay3' incorporates: + * UnitDelay: '/UnitDelay5' */ rtDW->UnitDelay3_DSTATE_o = rtDW->UnitDelay5_DSTATE; - /* Update for UnitDelay: '/UnitDelay5' */ + /* Update for UnitDelay: '/UnitDelay5' */ rtDW->UnitDelay5_DSTATE = rtDW->z_counterRawPrev; - /* Update for UnitDelay: '/UnitDelay1' */ + /* Update for UnitDelay: '/UnitDelay1' */ rtDW->UnitDelay1_DSTATE_n = rtb_RelationalOperator4_d; - /* End of Outputs for SubSystem: '/Raw_Motor_Speed_Estimation' */ + /* End of Outputs for SubSystem: '/Raw_Motor_Speed_Estimation' */ } - /* End of If: '/If2' */ + /* End of If: '/If2' */ - /* Outputs for Atomic SubSystem: '/Counter' */ + /* Outputs for Atomic SubSystem: '/Counter' */ - /* Constant: '/Constant6' incorporates: - * Constant: '/z_maxCntRst2' + /* Constant: '/Constant6' incorporates: + * Constant: '/z_maxCntRst2' */ rtb_Switch1_l = (int16_T) Counter(1, rtP->z_maxCntRst, rtb_LogicalOperator, &rtDW->Counter_e); - /* End of Outputs for SubSystem: '/Counter' */ + /* End of Outputs for SubSystem: '/Counter' */ - /* Switch: '/Switch2' incorporates: - * Constant: '/Constant4' - * Constant: '/z_maxCntRst' - * RelationalOperator: '/Relational Operator2' + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant4' + * Constant: '/z_maxCntRst' + * RelationalOperator: '/Relational Operator2' */ if (rtb_Switch1_l > rtP->z_maxCntRst) { - rtb_Switch2_k = 0; + Switch2 = 0; } else { - rtb_Switch2_k = rtDW->Divide11; + Switch2 = rtDW->Divide11; } - /* End of Switch: '/Switch2' */ + /* End of Switch: '/Switch2' */ - /* Abs: '/Abs5' */ - if (rtb_Switch2_k < 0) { - rtb_Abs5 = (int16_T)-rtb_Switch2_k; + /* Abs: '/Abs5' */ + if (Switch2 < 0) { + Abs5 = (int16_T)-Switch2; } else { - rtb_Abs5 = rtb_Switch2_k; + Abs5 = Switch2; } - /* End of Abs: '/Abs5' */ + /* End of Abs: '/Abs5' */ - /* Relay: '/n_commDeacv' */ - if (rtb_Abs5 >= rtP->n_commDeacvHi) { + /* Relay: '/n_commDeacv' */ + if (Abs5 >= rtP->n_commDeacvHi) { rtDW->n_commDeacv_Mode = true; } else { - if (rtb_Abs5 <= rtP->n_commAcvLo) { + if (Abs5 <= rtP->n_commAcvLo) { rtDW->n_commDeacv_Mode = false; } } - /* Logic: '/Logical Operator3' incorporates: - * Constant: '/b_angleMeasEna' - * Logic: '/Logical Operator1' - * Logic: '/Logical Operator2' - * Relay: '/n_commDeacv' + /* Logic: '/Logical Operator3' incorporates: + * Constant: '/b_angleMeasEna' + * Logic: '/Logical Operator1' + * Logic: '/Logical Operator2' + * Relay: '/n_commDeacv' */ rtb_LogicalOperator = (rtP->b_angleMeasEna || (rtDW->n_commDeacv_Mode && (!rtDW->dz_cntTrnsDet))); + /* UnitDelay: '/UnitDelay2' */ + rtb_RelationalOperator4_d = rtDW->UnitDelay2_DSTATE_c; + + /* UnitDelay: '/UnitDelay5' */ + rtb_UnitDelay5_e = rtDW->UnitDelay5_DSTATE_m; + /* DataTypeConversion: '/Data Type Conversion2' incorporates: * Inport: '/r_inpTgt' */ - rtb_DataTypeConversion2 = (int16_T)(rtU->r_inpTgt << 4); - - /* UnitDelay: '/UnitDelay2' */ - rtb_RelationalOperator4_d = rtDW->UnitDelay2_DSTATE_g; - - /* If: '/If2' incorporates: - * Constant: '/b_diagEna' - * Constant: '/CTRL_COMM2' - * Constant: '/t_errDequal' - * Constant: '/t_errQual' - * Logic: '/Logical Operator2' - * RelationalOperator: '/Relational Operator2' - * UnitDelay: '/UnitDelay2' - */ - if (rtP->b_diagEna && rtDW->UnitDelay2_DSTATE_g) { - /* Outputs for IfAction SubSystem: '/F02_Diagnostics' incorporates: - * ActionPort: '/Action Port' - */ - /* Switch: '/Switch3' incorporates: - * Abs: '/Abs4' - * Constant: '/n_stdStillDet' - * Constant: '/CTRL_COMM4' - * Constant: '/r_errInpTgtThres' - * Inport: '/b_motEna' - * Logic: '/Logical Operator1' - * RelationalOperator: '/Relational Operator9' - * RelationalOperator: '/Relational Operator7' - * S-Function (sfix_bitop): '/Bitwise Operator1' - * UnitDelay: '/UnitDelay' - * UnitDelay: '/UnitDelay4' - */ - if ((rtY->z_errCode & 4) != 0) { - rtb_RelationalOperator1_m = true; - } else { - if (rtDW->UnitDelay4_DSTATE_eu < 0) { - /* Abs: '/Abs4' incorporates: - * UnitDelay: '/UnitDelay4' - */ - rtb_Merge_f_idx_2 = (int16_T)-rtDW->UnitDelay4_DSTATE_eu; - } else { - /* Abs: '/Abs4' incorporates: - * UnitDelay: '/UnitDelay4' - */ - rtb_Merge_f_idx_2 = rtDW->UnitDelay4_DSTATE_eu; - } - - rtb_RelationalOperator1_m = (rtU->b_motEna && (rtb_Abs5 < - rtP->n_stdStillDet) && (rtb_Merge_f_idx_2 > rtP->r_errInpTgtThres)); - } - - /* End of Switch: '/Switch3' */ - - /* Sum: '/Sum' incorporates: - * Constant: '/CTRL_COMM' - * Constant: '/CTRL_COMM1' - * DataTypeConversion: '/Data Type Conversion3' - * Gain: '/g_Hb' - * Gain: '/g_Hb1' - * RelationalOperator: '/Relational Operator1' - * RelationalOperator: '/Relational Operator3' - */ - rtb_Sum_l = (uint8_T)(((uint32_T)((rtb_Sum == 7) << 1) + (rtb_Sum == 0)) + - (rtb_RelationalOperator1_m << 2)); - - /* Outputs for Atomic SubSystem: '/Debounce_Filter' */ - Debounce_Filter(rtb_Sum_l != 0, rtP->t_errQual, rtP->t_errDequal, - &rtDW->Merge_n, &rtDW->Debounce_Filter_f); - - /* End of Outputs for SubSystem: '/Debounce_Filter' */ - - /* Outputs for Atomic SubSystem: '/either_edge' */ - rtb_RelationalOperator1_m = either_edge(rtDW->Merge_n, &rtDW->either_edge_a); - - /* End of Outputs for SubSystem: '/either_edge' */ - - /* Switch: '/Switch1' incorporates: - * Constant: '/CTRL_COMM2' - * Constant: '/t_errDequal' - * Constant: '/t_errQual' - * RelationalOperator: '/Relational Operator2' - */ - if (rtb_RelationalOperator1_m) { - /* Outport: '/z_errCode' */ - rtY->z_errCode = rtb_Sum_l; - } - - /* End of Switch: '/Switch1' */ - /* End of Outputs for SubSystem: '/F02_Diagnostics' */ - } - - /* End of If: '/If2' */ - - /* If: '/If4' incorporates: - * UnitDelay: '/UnitDelay2' - */ - rtb_Sum2_h = rtDW->If4_ActiveSubsystem; - UnitDelay3 = -1; - if (rtDW->UnitDelay2_DSTATE_g) { - UnitDelay3 = 0; - } - - rtDW->If4_ActiveSubsystem = UnitDelay3; - if ((rtb_Sum2_h != UnitDelay3) && (rtb_Sum2_h == 0)) { - /* Disable for If: '/If2' */ - rtDW->If2_ActiveSubsystem = -1; - } - - if (UnitDelay3 == 0) { - /* Outputs for IfAction SubSystem: '/F03_Control_Mode_Manager' incorporates: - * ActionPort: '/Action Port' - */ - /* Logic: '/Logical Operator1' incorporates: - * Constant: '/b_cruiseCtrlEna' - * Constant: '/constant1' - * Inport: '/z_ctrlModReq' - * RelationalOperator: '/Relational Operator1' - */ - rtb_RelationalOperator1_m = ((rtU->z_ctrlModReq == 2) || - rtP->b_cruiseCtrlEna); - - /* Logic: '/Logical Operator2' incorporates: - * Constant: '/b_cruiseCtrlEna' - * Constant: '/constant' - * Inport: '/z_ctrlModReq' - * Logic: '/Logical Operator5' - * RelationalOperator: '/Relational Operator4' - */ - rtb_LogicalOperator2_p = ((rtU->z_ctrlModReq == 3) && (!rtP->b_cruiseCtrlEna)); - - /* Logic: '/Logical Operator4' incorporates: - * Constant: '/constant8' - * Inport: '/b_motEna' - * Inport: '/z_ctrlModReq' - * Logic: '/Logical Operator7' - * RelationalOperator: '/Relational Operator10' - */ - rtb_LogicalOperator4 = (rtDW->Merge_n || (!rtU->b_motEna) || - (rtU->z_ctrlModReq == 0)); - - /* Chart: '/F03_02_Control_Mode_Manager' incorporates: - * Constant: '/constant5' - * Inport: '/z_ctrlModReq' - * Logic: '/Logical Operator3' - * Logic: '/Logical Operator6' - * Logic: '/Logical Operator9' - * RelationalOperator: '/Relational Operator5' - */ - if (rtDW->is_active_c1_BLDC_controller == 0U) { - rtDW->is_active_c1_BLDC_controller = 1U; - rtDW->is_c1_BLDC_controller = IN_OPEN; - rtDW->z_ctrlMod = OPEN_MODE; - } else if (rtDW->is_c1_BLDC_controller == IN_ACTIVE) { - if (rtb_LogicalOperator4) { - rtDW->is_ACTIVE = IN_NO_ACTIVE_CHILD; - rtDW->is_c1_BLDC_controller = IN_OPEN; - rtDW->z_ctrlMod = OPEN_MODE; - } else { - switch (rtDW->is_ACTIVE) { - case IN_SPEED_MODE: - rtDW->z_ctrlMod = SPD_MODE; - if (!rtb_RelationalOperator1_m) { - rtDW->is_ACTIVE = IN_NO_ACTIVE_CHILD; - if (rtb_LogicalOperator2_p) { - rtDW->is_ACTIVE = IN_TORQUE_MODE; - rtDW->z_ctrlMod = TRQ_MODE; - } else { - rtDW->is_ACTIVE = IN_VOLTAGE_MODE; - rtDW->z_ctrlMod = VLT_MODE; - } - } - break; - - case IN_TORQUE_MODE: - rtDW->z_ctrlMod = TRQ_MODE; - if (!rtb_LogicalOperator2_p) { - rtDW->is_ACTIVE = IN_NO_ACTIVE_CHILD; - if (rtb_RelationalOperator1_m) { - rtDW->is_ACTIVE = IN_SPEED_MODE; - rtDW->z_ctrlMod = SPD_MODE; - } else { - rtDW->is_ACTIVE = IN_VOLTAGE_MODE; - rtDW->z_ctrlMod = VLT_MODE; - } - } - break; - - default: - rtDW->z_ctrlMod = VLT_MODE; - if (rtb_LogicalOperator2_p || rtb_RelationalOperator1_m) { - rtDW->is_ACTIVE = IN_NO_ACTIVE_CHILD; - if (rtb_LogicalOperator2_p) { - rtDW->is_ACTIVE = IN_TORQUE_MODE; - rtDW->z_ctrlMod = TRQ_MODE; - } else if (rtb_RelationalOperator1_m) { - rtDW->is_ACTIVE = IN_SPEED_MODE; - rtDW->z_ctrlMod = SPD_MODE; - } else { - rtDW->is_ACTIVE = IN_VOLTAGE_MODE; - rtDW->z_ctrlMod = VLT_MODE; - } - } - break; - } - } - } else { - rtDW->z_ctrlMod = OPEN_MODE; - if ((!rtb_LogicalOperator4) && ((rtU->z_ctrlModReq == 1) || - rtb_RelationalOperator1_m || rtb_LogicalOperator2_p)) { - rtDW->is_c1_BLDC_controller = IN_ACTIVE; - if (rtb_LogicalOperator2_p) { - rtDW->is_ACTIVE = IN_TORQUE_MODE; - rtDW->z_ctrlMod = TRQ_MODE; - } else if (rtb_RelationalOperator1_m) { - rtDW->is_ACTIVE = IN_SPEED_MODE; - rtDW->z_ctrlMod = SPD_MODE; - } else { - rtDW->is_ACTIVE = IN_VOLTAGE_MODE; - rtDW->z_ctrlMod = VLT_MODE; - } - } - } - - /* End of Chart: '/F03_02_Control_Mode_Manager' */ - - /* If: '/If1' incorporates: - * Constant: '/z_ctrlTypSel' - * Inport: '/r_inpTgt' - * Saturate: '/Saturation' - */ - if (rtP->z_ctrlTypSel == 2) { - /* Outputs for IfAction SubSystem: '/FOC_Control_Type' incorporates: - * ActionPort: '/Action Port' - */ - /* SignalConversion: '/TmpSignal ConversionAtSelectorInport1' incorporates: - * Constant: '/Vd_max' - * Constant: '/constant1' - * Constant: '/i_max' - * Constant: '/n_max' - */ - tmp[0] = 0; - tmp[1] = rtP->Vd_max; - tmp[2] = rtP->n_max; - tmp[3] = rtP->i_max; - - /* End of Outputs for SubSystem: '/FOC_Control_Type' */ - - /* Saturate: '/Saturation' */ - if (rtb_DataTypeConversion2 > 16000) { - rtb_Merge = 16000; - } else if (rtb_DataTypeConversion2 < -16000) { - rtb_Merge = -16000; - } else { - rtb_Merge = rtb_DataTypeConversion2; - } - - /* Outputs for IfAction SubSystem: '/FOC_Control_Type' incorporates: - * ActionPort: '/Action Port' - */ - /* Product: '/Divide1' incorporates: - * Inport: '/z_ctrlModReq' - * Product: '/Divide4' - * Selector: '/Selector' - */ - rtb_Merge = (int16_T)(((uint16_T)((tmp[rtU->z_ctrlModReq] << 5) / 125) * - rtb_Merge) >> 12); - - /* End of Outputs for SubSystem: '/FOC_Control_Type' */ - } else if (rtb_DataTypeConversion2 > 16000) { - /* Outputs for IfAction SubSystem: '/Default_Control_Type' incorporates: - * ActionPort: '/Action Port' - */ - /* Saturate: '/Saturation' incorporates: - * Inport: '/r_inpTgt' - */ - rtb_Merge = 16000; - - /* End of Outputs for SubSystem: '/Default_Control_Type' */ - } else if (rtb_DataTypeConversion2 < -16000) { - /* Outputs for IfAction SubSystem: '/Default_Control_Type' incorporates: - * ActionPort: '/Action Port' - */ - /* Saturate: '/Saturation' incorporates: - * Inport: '/r_inpTgt' - */ - rtb_Merge = -16000; - - /* End of Outputs for SubSystem: '/Default_Control_Type' */ - } else { - /* Outputs for IfAction SubSystem: '/Default_Control_Type' incorporates: - * ActionPort: '/Action Port' - */ - rtb_Merge = rtb_DataTypeConversion2; - - /* End of Outputs for SubSystem: '/Default_Control_Type' */ - } - - /* End of If: '/If1' */ - - /* If: '/If2' incorporates: - * Inport: '/r_inpTgtScaRaw' - */ - rtb_Sum2_h = rtDW->If2_ActiveSubsystem; - UnitDelay3 = (int8_T)!(rtDW->z_ctrlMod == 0); - rtDW->If2_ActiveSubsystem = UnitDelay3; - switch (UnitDelay3) { - case 0: - if (UnitDelay3 != rtb_Sum2_h) { - /* SystemReset for IfAction SubSystem: '/Open_Mode' incorporates: - * ActionPort: '/Action Port' - */ - /* SystemReset for Atomic SubSystem: '/rising_edge_init' */ - /* SystemReset for If: '/If2' incorporates: - * UnitDelay: '/UnitDelay' - * UnitDelay: '/UnitDelay' - */ - rtDW->UnitDelay_DSTATE_b = true; - - /* End of SystemReset for SubSystem: '/rising_edge_init' */ - - /* SystemReset for Atomic SubSystem: '/Rate_Limiter' */ - rtDW->UnitDelay_DSTATE = 0; - - /* End of SystemReset for SubSystem: '/Rate_Limiter' */ - /* End of SystemReset for SubSystem: '/Open_Mode' */ - } - - /* Outputs for IfAction SubSystem: '/Open_Mode' incorporates: - * ActionPort: '/Action Port' - */ - /* DataTypeConversion: '/Data Type Conversion' incorporates: - * UnitDelay: '/UnitDelay4' - */ - rtb_Gain3 = rtDW->UnitDelay4_DSTATE_eu << 12; - rtb_DataTypeConversion = (rtb_Gain3 & 134217728) != 0 ? rtb_Gain3 | - -134217728 : rtb_Gain3 & 134217727; - - /* Outputs for Atomic SubSystem: '/rising_edge_init' */ - /* UnitDelay: '/UnitDelay' */ - rtb_RelationalOperator1_m = rtDW->UnitDelay_DSTATE_b; - - /* Update for UnitDelay: '/UnitDelay' incorporates: - * Constant: '/Constant' - */ - rtDW->UnitDelay_DSTATE_b = false; - - /* End of Outputs for SubSystem: '/rising_edge_init' */ - - /* Outputs for Atomic SubSystem: '/Rate_Limiter' */ - /* Switch: '/Switch1' incorporates: - * UnitDelay: '/UnitDelay' - */ - if (rtb_RelationalOperator1_m) { - rtb_Switch1 = rtb_DataTypeConversion; - } else { - rtb_Switch1 = rtDW->UnitDelay_DSTATE; - } - - /* End of Switch: '/Switch1' */ - - /* Sum: '/Sum1' */ - rtb_Gain3 = -rtb_Switch1; - rtb_Sum1 = (rtb_Gain3 & 134217728) != 0 ? rtb_Gain3 | -134217728 : - rtb_Gain3 & 134217727; - - /* Switch: '/Switch2' incorporates: - * Constant: '/dV_openRate' - * RelationalOperator: '/LowerRelop1' - */ - if (rtb_Sum1 > rtP->dV_openRate) { - rtb_Sum1 = rtP->dV_openRate; - } else { - /* Gain: '/Gain3' */ - rtb_Gain3 = -rtP->dV_openRate; - rtb_Gain3 = (rtb_Gain3 & 134217728) != 0 ? rtb_Gain3 | -134217728 : - rtb_Gain3 & 134217727; - - /* Switch: '/Switch' incorporates: - * RelationalOperator: '/UpperRelop' - */ - if (rtb_Sum1 < rtb_Gain3) { - rtb_Sum1 = rtb_Gain3; - } - - /* End of Switch: '/Switch' */ - } - - /* End of Switch: '/Switch2' */ - - /* Sum: '/Sum2' */ - rtb_Gain3 = rtb_Sum1 + rtb_Switch1; - rtb_Switch1 = (rtb_Gain3 & 134217728) != 0 ? rtb_Gain3 | -134217728 : - rtb_Gain3 & 134217727; - - /* Switch: '/Switch2' */ - if (rtb_RelationalOperator1_m) { - /* Update for UnitDelay: '/UnitDelay' */ - rtDW->UnitDelay_DSTATE = rtb_DataTypeConversion; - } else { - /* Update for UnitDelay: '/UnitDelay' */ - rtDW->UnitDelay_DSTATE = rtb_Switch1; - } - - /* End of Switch: '/Switch2' */ - /* End of Outputs for SubSystem: '/Rate_Limiter' */ - - /* DataTypeConversion: '/Data Type Conversion1' */ - rtDW->Merge1 = (int16_T)(rtb_Switch1 >> 12); - - /* End of Outputs for SubSystem: '/Open_Mode' */ - break; - - case 1: - /* Outputs for IfAction SubSystem: '/Default_Mode' incorporates: - * ActionPort: '/Action Port' - */ - rtDW->Merge1 = rtb_Merge; - - /* End of Outputs for SubSystem: '/Default_Mode' */ - break; - } - - /* End of If: '/If2' */ - /* End of Outputs for SubSystem: '/F03_Control_Mode_Manager' */ - } - - /* End of If: '/If4' */ - - /* UnitDelay: '/UnitDelay5' */ - rtb_RelationalOperator1_m = rtDW->UnitDelay5_DSTATE_l; + DataTypeConversion2 = (int16_T)(rtU->r_inpTgt << 4); /* Saturate: '/Saturation' incorporates: * Inport: '/i_phaAB' @@ -1695,207 +1291,108 @@ void BLDC_controller_step(RT_MODEL *const rtM) /* End of Saturate: '/Saturation1' */ - /* If: '/If1' incorporates: - * Constant: '/b_angleMeasEna' + /* If: '/If1' incorporates: + * Constant: '/b_angleMeasEna' */ if (!rtP->b_angleMeasEna) { - /* Outputs for IfAction SubSystem: '/F01_05_Electrical_Angle_Estimation' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/F01_05_Electrical_Angle_Estimation' incorporates: + * ActionPort: '/Action Port' */ - /* Switch: '/Switch2' incorporates: - * Constant: '/Constant16' - * Product: '/Divide1' - * Product: '/Divide3' - * RelationalOperator: '/Relational Operator7' - * Sum: '/Sum3' - * Switch: '/Switch3' + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant16' + * Product: '/Divide1' + * Product: '/Divide3' + * RelationalOperator: '/Relational Operator7' + * Sum: '/Sum3' + * Switch: '/Switch3' */ if (rtb_LogicalOperator) { - /* MinMax: '/MinMax' */ - rtb_Merge = rtb_Switch1_l; - if (!(rtb_Merge < rtDW->z_counterRawPrev)) { - rtb_Merge = rtDW->z_counterRawPrev; + /* MinMax: '/MinMax' */ + rtb_Merge_m = rtb_Switch1_l; + if (!(rtb_Merge_m < rtDW->z_counterRawPrev)) { + rtb_Merge_m = rtDW->z_counterRawPrev; } - /* End of MinMax: '/MinMax' */ + /* End of MinMax: '/MinMax' */ - /* Switch: '/Switch3' incorporates: - * Constant: '/vec_hallToPos' - * Constant: '/Constant16' - * RelationalOperator: '/Relational Operator7' - * Selector: '/Selector' - * Sum: '/Sum1' + /* Switch: '/Switch3' incorporates: + * Constant: '/vec_hallToPos' + * Constant: '/Constant16' + * RelationalOperator: '/Relational Operator7' + * Selector: '/Selector' + * Sum: '/Sum1' */ if (rtDW->Switch2_e == 1) { - rtb_Sum2_h = rtConstP.vec_hallToPos_Value[rtb_Sum]; + rtb_Sum2_h = rtConstP.vec_hallToPos_Value[Sum]; } else { - rtb_Sum2_h = (int8_T)(rtConstP.vec_hallToPos_Value[rtb_Sum] + 1); + rtb_Sum2_h = (int8_T)(rtConstP.vec_hallToPos_Value[Sum] + 1); } - rtb_Merge = (int16_T)(((int16_T)((int16_T)((rtb_Merge << 14) / + rtb_Merge_m = (int16_T)(((int16_T)((int16_T)((rtb_Merge_m << 14) / rtDW->z_counterRawPrev) * rtDW->Switch2_e) + (rtb_Sum2_h << 14)) >> 2); } else { if (rtDW->Switch2_e == 1) { - /* Switch: '/Switch3' incorporates: - * Constant: '/vec_hallToPos' - * Selector: '/Selector' + /* Switch: '/Switch3' incorporates: + * Constant: '/vec_hallToPos' + * Selector: '/Selector' */ - rtb_Sum2_h = rtConstP.vec_hallToPos_Value[rtb_Sum]; + rtb_Sum2_h = rtConstP.vec_hallToPos_Value[Sum]; } else { - /* Switch: '/Switch3' incorporates: - * Constant: '/vec_hallToPos' - * Selector: '/Selector' - * Sum: '/Sum1' + /* Switch: '/Switch3' incorporates: + * Constant: '/vec_hallToPos' + * Selector: '/Selector' + * Sum: '/Sum1' */ - rtb_Sum2_h = (int8_T)(rtConstP.vec_hallToPos_Value[rtb_Sum] + 1); + rtb_Sum2_h = (int8_T)(rtConstP.vec_hallToPos_Value[Sum] + 1); } - rtb_Merge = (int16_T)(rtb_Sum2_h << 12); + rtb_Merge_m = (int16_T)(rtb_Sum2_h << 12); } - /* End of Switch: '/Switch2' */ + /* End of Switch: '/Switch2' */ - /* MinMax: '/MinMax1' incorporates: - * Constant: '/Constant1' + /* MinMax: '/MinMax1' incorporates: + * Constant: '/Constant1' */ - if (!(rtb_Merge > 0)) { - rtb_Merge = 0; + if (!(rtb_Merge_m > 0)) { + rtb_Merge_m = 0; } - /* End of MinMax: '/MinMax1' */ + /* End of MinMax: '/MinMax1' */ - /* SignalConversion: '/Signal Conversion2' incorporates: - * Product: '/Divide2' + /* SignalConversion: '/Signal Conversion2' incorporates: + * Product: '/Divide2' */ - rtb_Merge = (int16_T)((15 * rtb_Merge) >> 4); + rtb_Merge_m = (int16_T)((15 * rtb_Merge_m) >> 4); - /* End of Outputs for SubSystem: '/F01_05_Electrical_Angle_Estimation' */ + /* End of Outputs for SubSystem: '/F01_05_Electrical_Angle_Estimation' */ } else { - /* Outputs for IfAction SubSystem: '/F01_06_Electrical_Angle_Measurement' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/F01_06_Electrical_Angle_Measurement' incorporates: + * ActionPort: '/Action Port' */ - /* Sum: '/Sum1' incorporates: - * Constant: '/Constant2' - * Constant: '/n_polePairs' + /* Sum: '/Sum1' incorporates: + * Constant: '/Constant2' + * Constant: '/n_polePairs' * Inport: '/a_mechAngle' - * Product: '/Divide' + * Product: '/Divide' */ - rtb_DataTypeConversion = rtU->a_mechAngle * rtP->n_polePairs - 480; + rtb_Sum1_jt = rtU->a_mechAngle * rtP->n_polePairs - 480; - /* DataTypeConversion: '/Data Type Conversion20' incorporates: - * Constant: '/a_elecPeriod' - * Product: '/Divide2' - * Product: '/Divide3' - * Sum: '/Sum3' + /* DataTypeConversion: '/Data Type Conversion20' incorporates: + * Constant: '/a_elecPeriod' + * Product: '/Divide2' + * Product: '/Divide3' + * Sum: '/Sum3' */ - rtb_Merge = (int16_T)((int16_T)(rtb_DataTypeConversion - ((int16_T)((int16_T) - div_nde_s32_floor(rtb_DataTypeConversion, 5760) * 360) << 4)) << 2); + rtb_Merge_m = (int16_T)((int16_T)(rtb_Sum1_jt - ((int16_T)((int16_T) + div_nde_s32_floor(rtb_Sum1_jt, 5760) * 360) << 4)) << 2); - /* End of Outputs for SubSystem: '/F01_06_Electrical_Angle_Measurement' */ + /* End of Outputs for SubSystem: '/F01_06_Electrical_Angle_Measurement' */ } - /* End of If: '/If1' */ + /* End of If: '/If1' */ - /* If: '/If3' incorporates: - * Constant: '/CTRL_COMM2' - * Constant: '/b_fieldWeakEna' - * Constant: '/z_ctrlTypSel' - * Logic: '/Logical Operator1' - * RelationalOperator: '/Relational Operator1' - * UnitDelay: '/UnitDelay5' - */ - if (rtP->b_fieldWeakEna && rtDW->UnitDelay5_DSTATE_l && (rtP->z_ctrlTypSel != - 0)) { - /* Outputs for IfAction SubSystem: '/F04_Field_Weakening' incorporates: - * ActionPort: '/Action Port' - */ - /* Abs: '/Abs5' */ - if (rtb_DataTypeConversion2 < 0) { - rtb_DataTypeConversion2 = (int16_T)-rtb_DataTypeConversion2; - } - - /* End of Abs: '/Abs5' */ - - /* Switch: '/Switch2' incorporates: - * Constant: '/r_fieldWeakHi' - * Constant: '/r_fieldWeakLo' - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' - * Switch: '/Switch' - */ - if (rtb_DataTypeConversion2 > rtP->r_fieldWeakHi) { - rtb_DataTypeConversion2 = rtP->r_fieldWeakHi; - } else { - if (rtb_DataTypeConversion2 < rtP->r_fieldWeakLo) { - /* Switch: '/Switch' incorporates: - * Constant: '/r_fieldWeakLo' - */ - rtb_DataTypeConversion2 = rtP->r_fieldWeakLo; - } - } - - /* End of Switch: '/Switch2' */ - - /* Switch: '/Switch2' incorporates: - * Constant: '/CTRL_COMM2' - * Constant: '/a_phaAdvMax' - * Constant: '/id_fieldWeakMax' - * RelationalOperator: '/Relational Operator1' - */ - if (rtP->z_ctrlTypSel == 2) { - rtb_Merge_f_idx_2 = rtP->id_fieldWeakMax; - } else { - rtb_Merge_f_idx_2 = rtP->a_phaAdvMax; - } - - /* End of Switch: '/Switch2' */ - - /* Switch: '/Switch2' incorporates: - * Constant: '/n_fieldWeakAuthHi' - * Constant: '/n_fieldWeakAuthLo' - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' - * Switch: '/Switch' - */ - if (rtb_Abs5 > rtP->n_fieldWeakAuthHi) { - rtb_Switch2_l = rtP->n_fieldWeakAuthHi; - } else if (rtb_Abs5 < rtP->n_fieldWeakAuthLo) { - /* Switch: '/Switch' incorporates: - * Constant: '/n_fieldWeakAuthLo' - */ - rtb_Switch2_l = rtP->n_fieldWeakAuthLo; - } else { - rtb_Switch2_l = rtb_Abs5; - } - - /* End of Switch: '/Switch2' */ - - /* Product: '/Divide3' incorporates: - * Constant: '/n_fieldWeakAuthHi' - * Constant: '/n_fieldWeakAuthLo' - * Constant: '/r_fieldWeakHi' - * Constant: '/r_fieldWeakLo' - * Product: '/Divide1' - * Product: '/Divide14' - * Product: '/Divide2' - * Sum: '/Sum1' - * Sum: '/Sum2' - * Sum: '/Sum3' - * Sum: '/Sum4' - */ - rtDW->Divide3 = (int16_T)(((uint16_T)(((uint32_T)(uint16_T)(((int16_T) - (rtb_DataTypeConversion2 - rtP->r_fieldWeakLo) << 15) / (int16_T) - (rtP->r_fieldWeakHi - rtP->r_fieldWeakLo)) * (uint16_T)(((int16_T) - (rtb_Switch2_l - rtP->n_fieldWeakAuthLo) << 15) / (int16_T) - (rtP->n_fieldWeakAuthHi - rtP->n_fieldWeakAuthLo))) >> 15) * - rtb_Merge_f_idx_2) >> 15); - - /* End of Outputs for SubSystem: '/F04_Field_Weakening' */ - } - - /* End of If: '/If3' */ - - /* If: '/If1' incorporates: + /* If: '/If1' incorporates: * Constant: '/z_ctrlTypSel' */ rtb_Sum2_h = rtDW->If1_ActiveSubsystem; @@ -1906,89 +1403,61 @@ void BLDC_controller_step(RT_MODEL *const rtM) rtDW->If1_ActiveSubsystem = UnitDelay3; if ((rtb_Sum2_h != UnitDelay3) && (rtb_Sum2_h == 0)) { - /* Disable for If: '/If2' */ + /* Disable for If: '/If2' */ if (rtDW->If2_ActiveSubsystem_a == 0) { - /* Disable for Outport: '/iq' */ + /* Disable for Outport: '/iq' */ rtDW->DataTypeConversion[0] = 0; - /* Disable for Outport: '/id' */ + /* Disable for Outport: '/iqAbs' */ + rtDW->Abs5_h = 0; + + /* Disable for Outport: '/id' */ rtDW->DataTypeConversion[1] = 0; } rtDW->If2_ActiveSubsystem_a = -1; - /* End of Disable for If: '/If2' */ + /* End of Disable for If: '/If2' */ - /* Disable for If: '/If1' */ - if (rtDW->If1_ActiveSubsystem_e == 0) { - /* Disable for SwitchCase: '/Switch Case' */ - rtDW->SwitchCase_ActiveSubsystem = -1; - } + /* Disable for Outport: '/r_sin' */ + rtDW->r_sin_M1 = 0; - rtDW->If1_ActiveSubsystem_e = -1; + /* Disable for Outport: '/r_cos' */ + rtDW->r_cos_M1 = 0; - /* End of Disable for If: '/If1' */ - - /* Disable for Outport: '/V_phaABC_FOC' */ - rtDW->Gain4[0] = 0; - rtDW->Gain4[1] = 0; - rtDW->Gain4[2] = 0; - - /* Disable for Outport: '/iq' */ + /* Disable for Outport: '/iq' */ rtDW->DataTypeConversion[0] = 0; - /* Disable for Outport: '/id' */ + /* Disable for Outport: '/id' */ rtDW->DataTypeConversion[1] = 0; + + /* Disable for Outport: '/iqAbs' */ + rtDW->Abs5_h = 0; } if (UnitDelay3 == 0) { - if (0 != rtb_Sum2_h) { - /* InitializeConditions for IfAction SubSystem: '/F05_Field_Oriented_Control' incorporates: - * ActionPort: '/Action Port' - */ - /* InitializeConditions for If: '/If1' incorporates: - * UnitDelay: '/UnitDelay4' - */ - rtDW->UnitDelay4_DSTATE_h = 0; - - /* End of InitializeConditions for SubSystem: '/F05_Field_Oriented_Control' */ - } - - /* Outputs for IfAction SubSystem: '/F05_Field_Oriented_Control' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/Clarke_Park_Transform_Forward' incorporates: + * ActionPort: '/Action Port' */ - /* Abs: '/Abs1' */ - if (rtDW->Merge1 < 0) { - rtb_Switch2_l = (int16_T)-rtDW->Merge1; - } else { - rtb_Switch2_l = rtDW->Merge1; - } - - /* End of Abs: '/Abs1' */ - - /* Gain: '/toNegative' */ - rtb_toNegative = (int16_T)-rtDW->Divide3; - - /* If: '/If1' incorporates: - * Constant: '/z_selPhaCurMeasABC' + /* If: '/If1' incorporates: + * Constant: '/z_selPhaCurMeasABC' */ if (rtP->z_selPhaCurMeasABC == 0) { - /* Outputs for IfAction SubSystem: '/Clarke_PhasesAB' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/Clarke_PhasesAB' incorporates: + * ActionPort: '/Action Port' */ - /* Gain: '/Gain4' */ + /* Gain: '/Gain4' */ rtb_Gain3 = 18919 * rtb_Saturation; - /* Gain: '/Gain2' */ - rtb_DataTypeConversion = 18919 * rtb_Saturation1; + /* Gain: '/Gain2' */ + rtb_Sum1_jt = 18919 * rtb_Saturation1; - /* Sum: '/Sum1' incorporates: - * Gain: '/Gain2' - * Gain: '/Gain4' + /* Sum: '/Sum1' incorporates: + * Gain: '/Gain2' + * Gain: '/Gain4' */ rtb_Gain3 = (((rtb_Gain3 < 0 ? 32767 : 0) + rtb_Gain3) >> 15) + (int16_T) - (((rtb_DataTypeConversion < 0 ? 16383 : 0) + rtb_DataTypeConversion) >> - 14); + (((rtb_Sum1_jt < 0 ? 16383 : 0) + rtb_Sum1_jt) >> 14); if (rtb_Gain3 > 32767) { rtb_Gain3 = 32767; } else { @@ -1997,15 +1466,15 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - rtb_DataTypeConversion2 = (int16_T)rtb_Gain3; + rtb_Merge1 = (int16_T)rtb_Gain3; - /* End of Sum: '/Sum1' */ - /* End of Outputs for SubSystem: '/Clarke_PhasesAB' */ + /* End of Sum: '/Sum1' */ + /* End of Outputs for SubSystem: '/Clarke_PhasesAB' */ } else if (rtP->z_selPhaCurMeasABC == 1) { - /* Outputs for IfAction SubSystem: '/Clarke_PhasesBC' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/Clarke_PhasesBC' incorporates: + * ActionPort: '/Action Port' */ - /* Sum: '/Sum3' */ + /* Sum: '/Sum3' */ rtb_Gain3 = rtb_Saturation - rtb_Saturation1; if (rtb_Gain3 > 32767) { rtb_Gain3 = 32767; @@ -2015,14 +1484,13 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - /* Gain: '/Gain2' incorporates: - * Sum: '/Sum3' + /* Gain: '/Gain2' incorporates: + * Sum: '/Sum3' */ rtb_Gain3 *= 18919; - rtb_DataTypeConversion2 = (int16_T)(((rtb_Gain3 < 0 ? 32767 : 0) + - rtb_Gain3) >> 15); + rtb_Merge1 = (int16_T)(((rtb_Gain3 < 0 ? 32767 : 0) + rtb_Gain3) >> 15); - /* Sum: '/Sum1' */ + /* Sum: '/Sum1' */ rtb_Gain3 = -rtb_Saturation - rtb_Saturation1; if (rtb_Gain3 > 32767) { rtb_Gain3 = 32767; @@ -2034,25 +1502,24 @@ void BLDC_controller_step(RT_MODEL *const rtM) rtb_Saturation = (int16_T)rtb_Gain3; - /* End of Sum: '/Sum1' */ - /* End of Outputs for SubSystem: '/Clarke_PhasesBC' */ + /* End of Sum: '/Sum1' */ + /* End of Outputs for SubSystem: '/Clarke_PhasesBC' */ } else { - /* Outputs for IfAction SubSystem: '/Clarke_PhasesAC' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/Clarke_PhasesAC' incorporates: + * ActionPort: '/Action Port' */ - /* Gain: '/Gain4' */ + /* Gain: '/Gain4' */ rtb_Gain3 = 18919 * rtb_Saturation; - /* Gain: '/Gain2' */ - rtb_DataTypeConversion = 18919 * rtb_Saturation1; + /* Gain: '/Gain2' */ + rtb_Sum1_jt = 18919 * rtb_Saturation1; - /* Sum: '/Sum1' incorporates: - * Gain: '/Gain2' - * Gain: '/Gain4' + /* Sum: '/Sum1' incorporates: + * Gain: '/Gain2' + * Gain: '/Gain4' */ rtb_Gain3 = -(((rtb_Gain3 < 0 ? 32767 : 0) + rtb_Gain3) >> 15) - (int16_T) - (((rtb_DataTypeConversion < 0 ? 16383 : 0) + rtb_DataTypeConversion) >> - 14); + (((rtb_Sum1_jt < 0 ? 16383 : 0) + rtb_Sum1_jt) >> 14); if (rtb_Gain3 > 32767) { rtb_Gain3 = 32767; } else { @@ -2061,19 +1528,25 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - rtb_DataTypeConversion2 = (int16_T)rtb_Gain3; + rtb_Merge1 = (int16_T)rtb_Gain3; - /* End of Sum: '/Sum1' */ - /* End of Outputs for SubSystem: '/Clarke_PhasesAC' */ + /* End of Sum: '/Sum1' */ + /* End of Outputs for SubSystem: '/Clarke_PhasesAC' */ } - /* End of If: '/If1' */ + /* End of If: '/If1' */ - /* PreLookup: '/a_elecAngle_XA' */ - rtb_Sum_l = plook_u8s16_evencka(rtb_Merge, 0, 128U, 180U); + /* PreLookup: '/a_elecAngle_XA' */ + rtb_a_elecAngle_XA_g = plook_u8s16_evencka(rtb_Merge_m, 0, 128U, 180U); - /* If: '/If2' incorporates: - * Constant: '/cf_currFilt' + /* Interpolation_n-D: '/r_sin_M1' */ + rtDW->r_sin_M1 = rtConstP.r_sin_M1_Table[rtb_a_elecAngle_XA_g]; + + /* Interpolation_n-D: '/r_cos_M1' */ + rtDW->r_cos_M1 = rtConstP.r_cos_M1_Table[rtb_a_elecAngle_XA_g]; + + /* If: '/If2' incorporates: + * Constant: '/cf_currFilt' * Inport: '/b_motEna' */ rtb_Sum2_h = rtDW->If2_ActiveSubsystem_a; @@ -2084,38 +1557,38 @@ void BLDC_controller_step(RT_MODEL *const rtM) rtDW->If2_ActiveSubsystem_a = UnitDelay3; if ((rtb_Sum2_h != UnitDelay3) && (rtb_Sum2_h == 0)) { - /* Disable for Outport: '/iq' */ + /* Disable for Outport: '/iq' */ rtDW->DataTypeConversion[0] = 0; - /* Disable for Outport: '/id' */ + /* Disable for Outport: '/iqAbs' */ + rtDW->Abs5_h = 0; + + /* Disable for Outport: '/id' */ rtDW->DataTypeConversion[1] = 0; } if (UnitDelay3 == 0) { if (0 != rtb_Sum2_h) { - /* SystemReset for IfAction SubSystem: '/Current_Filtering' incorporates: - * ActionPort: '/Action Port' + /* SystemReset for IfAction SubSystem: '/Current_Filtering' incorporates: + * ActionPort: '/Action Port' */ - /* SystemReset for Atomic SubSystem: '/Low_Pass_Filter' */ + /* SystemReset for Atomic SubSystem: '/Low_Pass_Filter' */ - /* SystemReset for If: '/If2' */ + /* SystemReset for If: '/If2' */ Low_Pass_Filter_Reset(&rtDW->Low_Pass_Filter_m); - /* End of SystemReset for SubSystem: '/Low_Pass_Filter' */ + /* End of SystemReset for SubSystem: '/Low_Pass_Filter' */ - /* End of SystemReset for SubSystem: '/Current_Filtering' */ + /* End of SystemReset for SubSystem: '/Current_Filtering' */ } - /* Sum: '/Sum6' incorporates: - * Interpolation_n-D: '/r_cos_M1' - * Interpolation_n-D: '/r_sin_M1' - * Product: '/Divide1' - * Product: '/Divide4' + /* Sum: '/Sum6' incorporates: + * Product: '/Divide1' + * Product: '/Divide4' */ - rtb_Gain3 = (int16_T)((rtb_DataTypeConversion2 * - rtConstP.r_cos_M1_Table[rtb_Sum_l]) >> 14) - (int16_T)((rtb_Saturation * - rtConstP.r_sin_M1_Table[rtb_Sum_l]) >> 14); + rtb_Gain3 = (int16_T)((rtb_Merge1 * rtDW->r_cos_M1) >> 14) - (int16_T) + ((rtb_Saturation * rtDW->r_sin_M1) >> 14); if (rtb_Gain3 > 32767) { rtb_Gain3 = 32767; } else { @@ -2124,25 +1597,22 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - /* Outputs for IfAction SubSystem: '/Current_Filtering' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/Current_Filtering' incorporates: + * ActionPort: '/Action Port' */ - /* SignalConversion: '/TmpSignal ConversionAtLow_Pass_FilterInport1' incorporates: - * Sum: '/Sum6' + /* SignalConversion: '/TmpSignal ConversionAtLow_Pass_FilterInport1' incorporates: + * Sum: '/Sum6' */ rtb_TmpSignalConversionAtLow_Pa[0] = (int16_T)rtb_Gain3; - /* End of Outputs for SubSystem: '/Current_Filtering' */ + /* End of Outputs for SubSystem: '/Current_Filtering' */ - /* Sum: '/Sum1' incorporates: - * Interpolation_n-D: '/r_cos_M1' - * Interpolation_n-D: '/r_sin_M1' - * Product: '/Divide2' - * Product: '/Divide3' + /* Sum: '/Sum1' incorporates: + * Product: '/Divide2' + * Product: '/Divide3' */ - rtb_Gain3 = (int16_T)((rtb_Saturation * rtConstP.r_cos_M1_Table[rtb_Sum_l]) - >> 14) + (int16_T)((rtb_DataTypeConversion2 * - rtConstP.r_sin_M1_Table[rtb_Sum_l]) >> 14); + rtb_Gain3 = (int16_T)((rtb_Saturation * rtDW->r_cos_M1) >> 14) + (int16_T) + ((rtb_Merge1 * rtDW->r_sin_M1) >> 14); if (rtb_Gain3 > 32767) { rtb_Gain3 = 32767; } else { @@ -2151,65 +1621,615 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - /* Outputs for IfAction SubSystem: '/Current_Filtering' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/Current_Filtering' incorporates: + * ActionPort: '/Action Port' */ - /* SignalConversion: '/TmpSignal ConversionAtLow_Pass_FilterInport1' incorporates: - * Sum: '/Sum1' + /* SignalConversion: '/TmpSignal ConversionAtLow_Pass_FilterInport1' incorporates: + * Sum: '/Sum1' */ rtb_TmpSignalConversionAtLow_Pa[1] = (int16_T)rtb_Gain3; - /* Outputs for Atomic SubSystem: '/Low_Pass_Filter' */ + /* Outputs for Atomic SubSystem: '/Low_Pass_Filter' */ Low_Pass_Filter(rtb_TmpSignalConversionAtLow_Pa, rtP->cf_currFilt, rtDW->DataTypeConversion, &rtDW->Low_Pass_Filter_m); - /* End of Outputs for SubSystem: '/Low_Pass_Filter' */ + /* End of Outputs for SubSystem: '/Low_Pass_Filter' */ - /* End of Outputs for SubSystem: '/Current_Filtering' */ + /* Abs: '/Abs5' incorporates: + * Constant: '/cf_currFilt' + */ + if (rtDW->DataTypeConversion[0] < 0) { + rtDW->Abs5_h = (int16_T)-rtDW->DataTypeConversion[0]; + } else { + rtDW->Abs5_h = rtDW->DataTypeConversion[0]; + } + + /* End of Abs: '/Abs5' */ + /* End of Outputs for SubSystem: '/Current_Filtering' */ } - /* End of If: '/If2' */ + /* End of If: '/If2' */ + /* End of Outputs for SubSystem: '/Clarke_Park_Transform_Forward' */ + } - /* If: '/If3' incorporates: - * Constant: '/Vd_max1' - * Constant: '/i_max' - * UnitDelay: '/UnitDelay5' + /* End of If: '/If1' */ + + /* Chart: '/Task_Scheduler' incorporates: + * UnitDelay: '/UnitDelay2' + * UnitDelay: '/UnitDelay5' + * UnitDelay: '/UnitDelay6' + */ + if (rtDW->UnitDelay2_DSTATE_c) { + /* Outputs for Function Call SubSystem: '/F02_Diagnostics' */ + /* If: '/If2' incorporates: + * Constant: '/CTRL_COMM2' + * Constant: '/t_errDequal' + * Constant: '/t_errQual' + * Constant: '/b_diagEna' + * RelationalOperator: '/Relational Operator2' */ - if (rtDW->UnitDelay5_DSTATE_l) { - /* Outputs for IfAction SubSystem: '/Motor_Limitations' incorporates: - * ActionPort: '/Action Port' + if (rtP->b_diagEna) { + /* Outputs for IfAction SubSystem: '/Diagnostics_Enabled' incorporates: + * ActionPort: '/Action Port' + */ + /* Switch: '/Switch3' incorporates: + * Abs: '/Abs4' + * Constant: '/n_stdStillDet' + * Constant: '/CTRL_COMM4' + * Constant: '/r_errInpTgtThres' + * Inport: '/b_motEna' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator9' + * RelationalOperator: '/Relational Operator7' + * S-Function (sfix_bitop): '/Bitwise Operator1' + * UnitDelay: '/UnitDelay' + * UnitDelay: '/UnitDelay4' + */ + if ((rtDW->UnitDelay_DSTATE_e & 4) != 0) { + rtb_RelationalOperator1_mv = true; + } else { + if (rtDW->UnitDelay4_DSTATE_eu < 0) { + /* Abs: '/Abs4' incorporates: + * UnitDelay: '/UnitDelay4' + */ + rtb_Saturation1 = (int16_T)-rtDW->UnitDelay4_DSTATE_eu; + } else { + /* Abs: '/Abs4' incorporates: + * UnitDelay: '/UnitDelay4' + */ + rtb_Saturation1 = rtDW->UnitDelay4_DSTATE_eu; + } + + rtb_RelationalOperator1_mv = (rtU->b_motEna && (Abs5 < + rtP->n_stdStillDet) && (rtb_Saturation1 > rtP->r_errInpTgtThres)); + } + + /* End of Switch: '/Switch3' */ + + /* Sum: '/Sum' incorporates: + * Constant: '/CTRL_COMM' + * Constant: '/CTRL_COMM1' + * DataTypeConversion: '/Data Type Conversion3' + * Gain: '/g_Hb' + * Gain: '/g_Hb1' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator3' + */ + rtb_a_elecAngle_XA_g = (uint8_T)(((uint32_T)((Sum == 7) << 1) + (Sum == 0)) + + (rtb_RelationalOperator1_mv << 2)); + + /* Outputs for Atomic SubSystem: '/Debounce_Filter' */ + Debounce_Filter(rtb_a_elecAngle_XA_g != 0, rtP->t_errQual, + rtP->t_errDequal, &rtDW->Merge_p, &rtDW->Debounce_Filter_k); + + /* End of Outputs for SubSystem: '/Debounce_Filter' */ + + /* Outputs for Atomic SubSystem: '/either_edge' */ + either_edge(rtDW->Merge_p, &rtb_RelationalOperator1_mv, + &rtDW->either_edge_i); + + /* End of Outputs for SubSystem: '/either_edge' */ + + /* Switch: '/Switch1' incorporates: + * Constant: '/CTRL_COMM2' + * Constant: '/t_errDequal' + * Constant: '/t_errQual' + * RelationalOperator: '/Relational Operator2' + */ + if (rtb_RelationalOperator1_mv) { + /* Outport: '/z_errCode' */ + rtY->z_errCode = rtb_a_elecAngle_XA_g; + } else { + /* Outport: '/z_errCode' incorporates: + * UnitDelay: '/UnitDelay' + */ + rtY->z_errCode = rtDW->UnitDelay_DSTATE_e; + } + + /* End of Switch: '/Switch1' */ + + /* Update for UnitDelay: '/UnitDelay' incorporates: + * Outport: '/z_errCode' + */ + rtDW->UnitDelay_DSTATE_e = rtY->z_errCode; + + /* End of Outputs for SubSystem: '/Diagnostics_Enabled' */ + } + + /* End of If: '/If2' */ + /* End of Outputs for SubSystem: '/F02_Diagnostics' */ + + /* Outputs for Function Call SubSystem: '/F03_Control_Mode_Manager' */ + /* Logic: '/Logical Operator4' incorporates: + * Constant: '/constant8' + * Inport: '/b_motEna' + * Inport: '/z_ctrlModReq' + * Logic: '/Logical Operator7' + * RelationalOperator: '/Relational Operator10' + */ + rtb_RelationalOperator1_mv = (rtDW->Merge_p || (!rtU->b_motEna) || + (rtU->z_ctrlModReq == 0)); + + /* Logic: '/Logical Operator1' incorporates: + * Constant: '/b_cruiseCtrlEna' + * Constant: '/constant1' + * Inport: '/z_ctrlModReq' + * RelationalOperator: '/Relational Operator1' + */ + rtb_LogicalOperator1_j = ((rtU->z_ctrlModReq == 2) || rtP->b_cruiseCtrlEna); + + /* Logic: '/Logical Operator2' incorporates: + * Constant: '/b_cruiseCtrlEna' + * Constant: '/constant' + * Inport: '/z_ctrlModReq' + * Logic: '/Logical Operator5' + * RelationalOperator: '/Relational Operator4' + */ + rtb_LogicalOperator2_p = ((rtU->z_ctrlModReq == 3) && (!rtP->b_cruiseCtrlEna)); + + /* Chart: '/F03_02_Control_Mode_Manager' incorporates: + * Constant: '/constant5' + * Inport: '/z_ctrlModReq' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator6' + * Logic: '/Logical Operator9' + * RelationalOperator: '/Relational Operator5' + */ + if (rtDW->is_active_c1_BLDC_controller == 0U) { + rtDW->is_active_c1_BLDC_controller = 1U; + rtDW->is_c1_BLDC_controller = IN_OPEN; + rtDW->z_ctrlMod = OPEN_MODE; + } else if (rtDW->is_c1_BLDC_controller == IN_ACTIVE) { + if (rtb_RelationalOperator1_mv) { + rtDW->is_ACTIVE = IN_NO_ACTIVE_CHILD; + rtDW->is_c1_BLDC_controller = IN_OPEN; + rtDW->z_ctrlMod = OPEN_MODE; + } else { + switch (rtDW->is_ACTIVE) { + case IN_SPEED_MODE: + rtDW->z_ctrlMod = SPD_MODE; + if (!rtb_LogicalOperator1_j) { + rtDW->is_ACTIVE = IN_NO_ACTIVE_CHILD; + if (rtb_LogicalOperator2_p) { + rtDW->is_ACTIVE = IN_TORQUE_MODE; + rtDW->z_ctrlMod = TRQ_MODE; + } else { + rtDW->is_ACTIVE = IN_VOLTAGE_MODE; + rtDW->z_ctrlMod = VLT_MODE; + } + } + break; + + case IN_TORQUE_MODE: + rtDW->z_ctrlMod = TRQ_MODE; + if (!rtb_LogicalOperator2_p) { + rtDW->is_ACTIVE = IN_NO_ACTIVE_CHILD; + if (rtb_LogicalOperator1_j) { + rtDW->is_ACTIVE = IN_SPEED_MODE; + rtDW->z_ctrlMod = SPD_MODE; + } else { + rtDW->is_ACTIVE = IN_VOLTAGE_MODE; + rtDW->z_ctrlMod = VLT_MODE; + } + } + break; + + default: + rtDW->z_ctrlMod = VLT_MODE; + if (rtb_LogicalOperator2_p || rtb_LogicalOperator1_j) { + rtDW->is_ACTIVE = IN_NO_ACTIVE_CHILD; + if (rtb_LogicalOperator2_p) { + rtDW->is_ACTIVE = IN_TORQUE_MODE; + rtDW->z_ctrlMod = TRQ_MODE; + } else if (rtb_LogicalOperator1_j) { + rtDW->is_ACTIVE = IN_SPEED_MODE; + rtDW->z_ctrlMod = SPD_MODE; + } else { + rtDW->is_ACTIVE = IN_VOLTAGE_MODE; + rtDW->z_ctrlMod = VLT_MODE; + } + } + break; + } + } + } else { + rtDW->z_ctrlMod = OPEN_MODE; + if ((!rtb_RelationalOperator1_mv) && ((rtU->z_ctrlModReq == 1) || + rtb_LogicalOperator1_j || rtb_LogicalOperator2_p)) { + rtDW->is_c1_BLDC_controller = IN_ACTIVE; + if (rtb_LogicalOperator2_p) { + rtDW->is_ACTIVE = IN_TORQUE_MODE; + rtDW->z_ctrlMod = TRQ_MODE; + } else if (rtb_LogicalOperator1_j) { + rtDW->is_ACTIVE = IN_SPEED_MODE; + rtDW->z_ctrlMod = SPD_MODE; + } else { + rtDW->is_ACTIVE = IN_VOLTAGE_MODE; + rtDW->z_ctrlMod = VLT_MODE; + } + } + } + + /* End of Chart: '/F03_02_Control_Mode_Manager' */ + + /* If: '/If1' incorporates: + * Constant: '/z_ctrlTypSel' + * Inport: '/r_inpTgt' + * Saturate: '/Saturation' + */ + if (rtP->z_ctrlTypSel == 2) { + /* Outputs for IfAction SubSystem: '/FOC_Control_Type' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion: '/TmpSignal ConversionAtSelectorInport1' incorporates: + * Constant: '/Vd_max' + * Constant: '/constant1' + * Constant: '/i_max' + * Constant: '/n_max' + */ + tmp[0] = 0; + tmp[1] = rtP->Vd_max; + tmp[2] = rtP->n_max; + tmp[3] = rtP->i_max; + + /* End of Outputs for SubSystem: '/FOC_Control_Type' */ + + /* Saturate: '/Saturation' */ + if (DataTypeConversion2 > 16000) { + DataTypeConversion2 = 16000; + } else { + if (DataTypeConversion2 < -16000) { + DataTypeConversion2 = -16000; + } + } + + /* Outputs for IfAction SubSystem: '/FOC_Control_Type' incorporates: + * ActionPort: '/Action Port' + */ + /* Product: '/Divide1' incorporates: + * Inport: '/z_ctrlModReq' + * Product: '/Divide4' + * Selector: '/Selector' + */ + rtb_Saturation = (int16_T)(((uint16_T)((tmp[rtU->z_ctrlModReq] << 5) / 125) + * DataTypeConversion2) >> 12); + + /* End of Outputs for SubSystem: '/FOC_Control_Type' */ + } else if (DataTypeConversion2 > 16000) { + /* Outputs for IfAction SubSystem: '/Default_Control_Type' incorporates: + * ActionPort: '/Action Port' + */ + /* Saturate: '/Saturation' incorporates: + * Inport: '/r_inpTgt' + */ + rtb_Saturation = 16000; + + /* End of Outputs for SubSystem: '/Default_Control_Type' */ + } else if (DataTypeConversion2 < -16000) { + /* Outputs for IfAction SubSystem: '/Default_Control_Type' incorporates: + * ActionPort: '/Action Port' + */ + /* Saturate: '/Saturation' incorporates: + * Inport: '/r_inpTgt' + */ + rtb_Saturation = -16000; + + /* End of Outputs for SubSystem: '/Default_Control_Type' */ + } else { + /* Outputs for IfAction SubSystem: '/Default_Control_Type' incorporates: + * ActionPort: '/Action Port' + */ + rtb_Saturation = DataTypeConversion2; + + /* End of Outputs for SubSystem: '/Default_Control_Type' */ + } + + /* End of If: '/If1' */ + + /* If: '/If2' incorporates: + * Inport: '/r_inpTgtScaRaw' + */ + rtb_Sum2_h = rtDW->If2_ActiveSubsystem_f; + UnitDelay3 = (int8_T)!(rtDW->z_ctrlMod == 0); + rtDW->If2_ActiveSubsystem_f = UnitDelay3; + switch (UnitDelay3) { + case 0: + if (UnitDelay3 != rtb_Sum2_h) { + /* SystemReset for IfAction SubSystem: '/Open_Mode' incorporates: + * ActionPort: '/Action Port' + */ + /* SystemReset for Atomic SubSystem: '/rising_edge_init' */ + /* SystemReset for If: '/If2' incorporates: + * UnitDelay: '/UnitDelay' + * UnitDelay: '/UnitDelay' + */ + rtDW->UnitDelay_DSTATE_b = true; + + /* End of SystemReset for SubSystem: '/rising_edge_init' */ + + /* SystemReset for Atomic SubSystem: '/Rate_Limiter' */ + rtDW->UnitDelay_DSTATE = 0; + + /* End of SystemReset for SubSystem: '/Rate_Limiter' */ + /* End of SystemReset for SubSystem: '/Open_Mode' */ + } + + /* Outputs for IfAction SubSystem: '/Open_Mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * UnitDelay: '/UnitDelay4' + */ + rtb_Gain3 = rtDW->UnitDelay4_DSTATE_eu << 12; + rtb_Sum1_jt = (rtb_Gain3 & 134217728) != 0 ? rtb_Gain3 | -134217728 : + rtb_Gain3 & 134217727; + + /* Outputs for Atomic SubSystem: '/rising_edge_init' */ + /* UnitDelay: '/UnitDelay' */ + rtb_RelationalOperator1_mv = rtDW->UnitDelay_DSTATE_b; + + /* Update for UnitDelay: '/UnitDelay' incorporates: + * Constant: '/Constant' + */ + rtDW->UnitDelay_DSTATE_b = false; + + /* End of Outputs for SubSystem: '/rising_edge_init' */ + + /* Outputs for Atomic SubSystem: '/Rate_Limiter' */ + /* Switch: '/Switch1' incorporates: + * UnitDelay: '/UnitDelay' + */ + if (rtb_RelationalOperator1_mv) { + rtb_Switch1 = rtb_Sum1_jt; + } else { + rtb_Switch1 = rtDW->UnitDelay_DSTATE; + } + + /* End of Switch: '/Switch1' */ + + /* Sum: '/Sum1' */ + rtb_Gain3 = -rtb_Switch1; + rtb_Sum1 = (rtb_Gain3 & 134217728) != 0 ? rtb_Gain3 | -134217728 : + rtb_Gain3 & 134217727; + + /* Switch: '/Switch2' incorporates: + * Constant: '/dV_openRate' + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_Sum1 > rtP->dV_openRate) { + rtb_Sum1 = rtP->dV_openRate; + } else { + /* Gain: '/Gain3' */ + rtb_Gain3 = -rtP->dV_openRate; + rtb_Gain3 = (rtb_Gain3 & 134217728) != 0 ? rtb_Gain3 | -134217728 : + rtb_Gain3 & 134217727; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + */ + if (rtb_Sum1 < rtb_Gain3) { + rtb_Sum1 = rtb_Gain3; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Sum: '/Sum2' */ + rtb_Gain3 = rtb_Sum1 + rtb_Switch1; + rtb_Switch1 = (rtb_Gain3 & 134217728) != 0 ? rtb_Gain3 | -134217728 : + rtb_Gain3 & 134217727; + + /* Switch: '/Switch2' */ + if (rtb_RelationalOperator1_mv) { + /* Update for UnitDelay: '/UnitDelay' */ + rtDW->UnitDelay_DSTATE = rtb_Sum1_jt; + } else { + /* Update for UnitDelay: '/UnitDelay' */ + rtDW->UnitDelay_DSTATE = rtb_Switch1; + } + + /* End of Switch: '/Switch2' */ + /* End of Outputs for SubSystem: '/Rate_Limiter' */ + + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW->Merge1 = (int16_T)(rtb_Switch1 >> 12); + + /* End of Outputs for SubSystem: '/Open_Mode' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Default_Mode' incorporates: + * ActionPort: '/Action Port' + */ + rtDW->Merge1 = rtb_Saturation; + + /* End of Outputs for SubSystem: '/Default_Mode' */ + break; + } + + /* End of If: '/If2' */ + + /* Abs: '/Abs1' */ + if (rtDW->Merge1 < 0) { + rtDW->Abs1 = (int16_T)-rtDW->Merge1; + } else { + rtDW->Abs1 = rtDW->Merge1; + } + + /* End of Abs: '/Abs1' */ + /* End of Outputs for SubSystem: '/F03_Control_Mode_Manager' */ + } else if (rtDW->UnitDelay5_DSTATE_m) { + /* Outputs for Function Call SubSystem: '/F04_Field_Weakening' */ + /* If: '/If3' incorporates: + * Constant: '/b_fieldWeakEna' + */ + if (rtP->b_fieldWeakEna) { + /* Outputs for IfAction SubSystem: '/Field_Weakening_Enabled' incorporates: + * ActionPort: '/Action Port' + */ + /* Abs: '/Abs5' */ + if (DataTypeConversion2 < 0) { + DataTypeConversion2 = (int16_T)-DataTypeConversion2; + } + + /* End of Abs: '/Abs5' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/r_fieldWeakHi' + * Constant: '/r_fieldWeakLo' + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (DataTypeConversion2 > rtP->r_fieldWeakHi) { + DataTypeConversion2 = rtP->r_fieldWeakHi; + } else { + if (DataTypeConversion2 < rtP->r_fieldWeakLo) { + /* Switch: '/Switch' incorporates: + * Constant: '/r_fieldWeakLo' + */ + DataTypeConversion2 = rtP->r_fieldWeakLo; + } + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/z_ctrlTypSel' + * Constant: '/CTRL_COMM2' + * Constant: '/a_phaAdvMax' + * Constant: '/id_fieldWeakMax' + * RelationalOperator: '/Relational Operator1' + */ + if (rtP->z_ctrlTypSel == 2) { + rtb_Saturation1 = rtP->id_fieldWeakMax; + } else { + rtb_Saturation1 = rtP->a_phaAdvMax; + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/n_fieldWeakAuthHi' + * Constant: '/n_fieldWeakAuthLo' + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (Abs5 > rtP->n_fieldWeakAuthHi) { + rtb_Saturation = rtP->n_fieldWeakAuthHi; + } else if (Abs5 < rtP->n_fieldWeakAuthLo) { + /* Switch: '/Switch' incorporates: + * Constant: '/n_fieldWeakAuthLo' + */ + rtb_Saturation = rtP->n_fieldWeakAuthLo; + } else { + rtb_Saturation = Abs5; + } + + /* End of Switch: '/Switch2' */ + + /* Product: '/Divide3' incorporates: + * Constant: '/n_fieldWeakAuthHi' + * Constant: '/n_fieldWeakAuthLo' + * Constant: '/r_fieldWeakHi' + * Constant: '/r_fieldWeakLo' + * Product: '/Divide1' + * Product: '/Divide14' + * Product: '/Divide2' + * Sum: '/Sum1' + * Sum: '/Sum2' + * Sum: '/Sum3' + * Sum: '/Sum4' + */ + rtDW->Divide3 = (int16_T)(((uint16_T)(((uint32_T)(uint16_T)(((int16_T) + (DataTypeConversion2 - rtP->r_fieldWeakLo) << 15) / (int16_T) + (rtP->r_fieldWeakHi - rtP->r_fieldWeakLo)) * (uint16_T)(((int16_T) + (rtb_Saturation - rtP->n_fieldWeakAuthLo) << 15) / (int16_T) + (rtP->n_fieldWeakAuthHi - rtP->n_fieldWeakAuthLo))) >> 15) * + rtb_Saturation1) >> 15); + + /* End of Outputs for SubSystem: '/Field_Weakening_Enabled' */ + } + + /* End of If: '/If3' */ + /* End of Outputs for SubSystem: '/F04_Field_Weakening' */ + + /* Outputs for Function Call SubSystem: '/Motor_Limitations' */ + /* If: '/If1' incorporates: + * Constant: '/z_ctrlTypSel' + * Constant: '/Vd_max1' + * Constant: '/i_max' + */ + rtb_Sum2_h = rtDW->If1_ActiveSubsystem_o; + UnitDelay3 = -1; + if (rtP->z_ctrlTypSel == 2) { + UnitDelay3 = 0; + } + + rtDW->If1_ActiveSubsystem_o = UnitDelay3; + if ((rtb_Sum2_h != UnitDelay3) && (rtb_Sum2_h == 0)) { + /* Disable for SwitchCase: '/Switch Case' */ + rtDW->SwitchCase_ActiveSubsystem_d = -1; + } + + if (UnitDelay3 == 0) { + /* Outputs for IfAction SubSystem: '/Motor_Limitations_Enabled' incorporates: + * ActionPort: '/Action Port' */ rtDW->Vd_max1 = rtP->Vd_max; - /* Gain: '/Gain3' incorporates: - * Constant: '/Vd_max1' + /* Gain: '/Gain3' incorporates: + * Constant: '/Vd_max1' */ rtDW->Gain3 = (int16_T)-rtDW->Vd_max1; - /* Interpolation_n-D: '/Vq_max_M1' incorporates: - * Abs: '/Abs5' - * PreLookup: '/Vq_max_XA' - * UnitDelay: '/UnitDelay4' + /* Interpolation_n-D: '/Vq_max_M1' incorporates: + * Abs: '/Abs5' + * PreLookup: '/Vq_max_XA' + * UnitDelay: '/UnitDelay4' */ - if (rtDW->UnitDelay4_DSTATE_h < 0) { - rtb_Merge_f_idx_2 = (int16_T)-rtDW->UnitDelay4_DSTATE_h; + if (rtDW->Switch1 < 0) { + rtb_Saturation1 = (int16_T)-rtDW->Switch1; } else { - rtb_Merge_f_idx_2 = rtDW->UnitDelay4_DSTATE_h; + rtb_Saturation1 = rtDW->Switch1; } - rtDW->Vq_max_M1 = rtP->Vq_max_M1[plook_u8s16_evencka(rtb_Merge_f_idx_2, + rtDW->Vq_max_M1 = rtP->Vq_max_M1[plook_u8s16_evencka(rtb_Saturation1, rtP->Vq_max_XA[0], (uint16_T)(rtP->Vq_max_XA[1] - rtP->Vq_max_XA[0]), 45U)]; - /* End of Interpolation_n-D: '/Vq_max_M1' */ + /* End of Interpolation_n-D: '/Vq_max_M1' */ - /* Gain: '/Gain5' */ + /* Gain: '/Gain5' */ rtDW->Gain5 = (int16_T)-rtDW->Vq_max_M1; rtDW->i_max = rtP->i_max; - /* Interpolation_n-D: '/iq_maxSca_M1' incorporates: - * Constant: '/i_max' - * Product: '/Divide4' + /* Interpolation_n-D: '/iq_maxSca_M1' incorporates: + * Constant: '/i_max' + * Product: '/Divide4' */ rtb_Gain3 = rtDW->Divide3 << 16; rtb_Gain3 = (rtb_Gain3 == MIN_int32_T) && (rtDW->i_max == -1) ? @@ -2222,202 +2242,37 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - /* Product: '/Divide1' incorporates: - * Interpolation_n-D: '/iq_maxSca_M1' - * PreLookup: '/iq_maxSca_XA' - * Product: '/Divide4' + /* Product: '/Divide1' incorporates: + * Interpolation_n-D: '/iq_maxSca_M1' + * PreLookup: '/iq_maxSca_XA' + * Product: '/Divide4' */ - rtDW->Divide1_a = (int16_T) + rtDW->Divide1_n = (int16_T) ((rtConstP.iq_maxSca_M1_Table[plook_u8u16_evencka((uint16_T)rtb_Gain3, 0U, 1311U, 49U)] * rtDW->i_max) >> 16); - /* Gain: '/Gain1' */ - rtDW->Gain1 = (int16_T)-rtDW->Divide1_a; + /* Gain: '/Gain1' */ + rtDW->Gain1 = (int16_T)-rtDW->Divide1_n; - /* SwitchCase: '/Switch Case' incorporates: - * Constant: '/n_max1' - * Constant: '/Constant1' - * Constant: '/cf_KbLimProt' - * Constant: '/cf_nKiLimProt' - * Constant: '/Constant' - * Constant: '/Constant1' - * Constant: '/cf_KbLimProt' - * Constant: '/cf_iqKiLimProt' - * Constant: '/cf_nKiLimProt' - * Sum: '/Sum1' - * Sum: '/Sum1' - * Sum: '/Sum2' + /* SwitchCase: '/Switch Case' incorporates: + * Constant: '/n_max1' + * Constant: '/Constant1' + * Constant: '/cf_KbLimProt' + * Constant: '/cf_nKiLimProt' + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/cf_KbLimProt' + * Constant: '/cf_iqKiLimProt' + * Constant: '/cf_nKiLimProt' + * Sum: '/Sum1' + * Sum: '/Sum1' + * Sum: '/Sum2' */ + rtb_Sum2_h = rtDW->SwitchCase_ActiveSubsystem_d; + UnitDelay3 = -1; switch (rtDW->z_ctrlMod) { case 1: - /* Abs: '/Abs5' */ - if (rtDW->DataTypeConversion[0] < 0) { - rtb_Merge_f_idx_2 = (int16_T)-rtDW->DataTypeConversion[0]; - } else { - rtb_Merge_f_idx_2 = rtDW->DataTypeConversion[0]; - } - - /* End of Abs: '/Abs5' */ - - /* Outputs for IfAction SubSystem: '/Voltage_Mode_Protection' incorporates: - * ActionPort: '/Action Port' - */ - - /* Outputs for Atomic SubSystem: '/I_backCalc_fixdt' */ - I_backCalc_fixdt((int16_T)(rtDW->Divide1_a - rtb_Merge_f_idx_2), - rtP->cf_iqKiLimProt, rtP->cf_KbLimProt, rtb_Switch2_l, - 0, &rtDW->Switch2_c, &rtDW->I_backCalc_fixdt_i); - - /* End of Outputs for SubSystem: '/I_backCalc_fixdt' */ - - /* Outputs for Atomic SubSystem: '/I_backCalc_fixdt1' */ - I_backCalc_fixdt((int16_T)(rtP->n_max - rtb_Abs5), rtP->cf_nKiLimProt, - rtP->cf_KbLimProt, rtb_Switch2_l, 0, &rtDW->Switch2_l, - &rtDW->I_backCalc_fixdt1); - - /* End of Outputs for SubSystem: '/I_backCalc_fixdt1' */ - - /* End of Outputs for SubSystem: '/Voltage_Mode_Protection' */ - break; - - case 2: - /* Outputs for IfAction SubSystem: '/Speed_Mode_Protection' incorporates: - * ActionPort: '/Action Port' - */ - /* Switch: '/Switch2' incorporates: - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' - * Switch: '/Switch' - */ - if (rtDW->DataTypeConversion[0] > rtDW->Divide1_a) { - rtb_Merge_f_idx_2 = rtDW->Divide1_a; - } else if (rtDW->DataTypeConversion[0] < rtDW->Gain1) { - /* Switch: '/Switch' */ - rtb_Merge_f_idx_2 = rtDW->Gain1; - } else { - rtb_Merge_f_idx_2 = rtDW->DataTypeConversion[0]; - } - - /* End of Switch: '/Switch2' */ - - /* Product: '/Divide1' incorporates: - * Constant: '/cf_iqKiLimProt' - * Sum: '/Sum3' - */ - rtDW->Divide1 = (int16_T)(rtb_Merge_f_idx_2 - rtDW->DataTypeConversion[0]) - * rtP->cf_iqKiLimProt; - - /* End of Outputs for SubSystem: '/Speed_Mode_Protection' */ - break; - - case 3: - /* Outputs for IfAction SubSystem: '/Torque_Mode_Protection' incorporates: - * ActionPort: '/Action Port' - */ - - /* Outputs for Atomic SubSystem: '/I_backCalc_fixdt' */ - I_backCalc_fixdt((int16_T)(rtP->n_max - rtb_Abs5), rtP->cf_nKiLimProt, - rtP->cf_KbLimProt, rtDW->Vq_max_M1, 0, &rtDW->Switch2, - &rtDW->I_backCalc_fixdt_g); - - /* End of Outputs for SubSystem: '/I_backCalc_fixdt' */ - - /* End of Outputs for SubSystem: '/Torque_Mode_Protection' */ - break; - } - - /* End of SwitchCase: '/Switch Case' */ - - /* Gain: '/Gain4' */ - rtDW->Gain4_c = (int16_T)-rtDW->i_max; - - /* End of Outputs for SubSystem: '/Motor_Limitations' */ - } - - /* End of If: '/If3' */ - - /* If: '/If1' incorporates: - * UnitDelay: '/UnitDelay6' - */ - rtb_Sum2_h = rtDW->If1_ActiveSubsystem_e; - UnitDelay3 = -1; - if (rtDW->UnitDelay6_DSTATE) { - UnitDelay3 = 0; - } - - rtDW->If1_ActiveSubsystem_e = UnitDelay3; - if ((rtb_Sum2_h != UnitDelay3) && (rtb_Sum2_h == 0)) { - /* Disable for SwitchCase: '/Switch Case' */ - rtDW->SwitchCase_ActiveSubsystem = -1; - } - - if (UnitDelay3 == 0) { - /* Outputs for IfAction SubSystem: '/FOC' incorporates: - * ActionPort: '/Action Port' - */ - /* If: '/If1' incorporates: - * Constant: '/cf_idKi1' - * Constant: '/cf_idKp1' - * Constant: '/constant1' - * Constant: '/constant2' - * Sum: '/Sum3' - */ - if (rtb_LogicalOperator) { - /* Outputs for IfAction SubSystem: '/Vd_Calculation' incorporates: - * ActionPort: '/Action Port' - */ - /* Switch: '/Switch2' incorporates: - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' - * Switch: '/Switch' - */ - if (rtb_toNegative > rtDW->i_max) { - rtb_toNegative = rtDW->i_max; - } else { - if (rtb_toNegative < rtDW->Gain4_c) { - /* Switch: '/Switch' */ - rtb_toNegative = rtDW->Gain4_c; - } - } - - /* End of Switch: '/Switch2' */ - - /* Sum: '/Sum3' */ - rtb_Gain3 = rtb_toNegative - rtDW->DataTypeConversion[1]; - if (rtb_Gain3 > 32767) { - rtb_Gain3 = 32767; - } else { - if (rtb_Gain3 < -32768) { - rtb_Gain3 = -32768; - } - } - - /* Outputs for Atomic SubSystem: '/PI_clamp_fixdt' */ - PI_clamp_fixdt((int16_T)rtb_Gain3, rtP->cf_idKp, rtP->cf_idKi, 0, - rtDW->Vd_max1, rtDW->Gain3, 0, &rtDW->Switch1, - &rtDW->PI_clamp_fixdt_k); - - /* End of Outputs for SubSystem: '/PI_clamp_fixdt' */ - - /* End of Outputs for SubSystem: '/Vd_Calculation' */ - } - - /* End of If: '/If1' */ - - /* SwitchCase: '/Switch Case' incorporates: - * Constant: '/cf_nKi' - * Constant: '/cf_nKp' - * Constant: '/cf_iqKi' - * Constant: '/cf_iqKp' - * Constant: '/constant2' - * Inport: '/r_inpTgtSca' - * Sum: '/Sum3' - * Sum: '/Sum2' - * UnitDelay: '/UnitDelay4' - */ - rtb_Sum2_h = rtDW->SwitchCase_ActiveSubsystem; - switch (rtDW->z_ctrlMod) { - case 1: + UnitDelay3 = 0; break; case 2: @@ -2427,257 +2282,533 @@ void BLDC_controller_step(RT_MODEL *const rtM) case 3: UnitDelay3 = 2; break; - - default: - UnitDelay3 = 3; - break; } - rtDW->SwitchCase_ActiveSubsystem = UnitDelay3; + rtDW->SwitchCase_ActiveSubsystem_d = UnitDelay3; switch (UnitDelay3) { case 0: - /* Outputs for IfAction SubSystem: '/Voltage_Mode' incorporates: - * ActionPort: '/Action Port' - */ - /* MinMax: '/MinMax' */ - if (!(rtb_Switch2_l < rtDW->Switch2_c)) { - rtb_Switch2_l = rtDW->Switch2_c; - } - - if (!(rtb_Switch2_l < rtDW->Switch2_l)) { - rtb_Switch2_l = rtDW->Switch2_l; - } - - /* End of MinMax: '/MinMax' */ - - /* Signum: '/SignDeltaU2' */ - if (rtDW->Merge1 < 0) { - rtb_Merge_f_idx_2 = -1; - } else { - rtb_Merge_f_idx_2 = (int16_T)(rtDW->Merge1 > 0); - } - - /* End of Signum: '/SignDeltaU2' */ - - /* Product: '/Divide1' */ - rtb_Saturation = (int16_T)(rtb_Switch2_l * rtb_Merge_f_idx_2); - - /* Switch: '/Switch2' incorporates: - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' - * Switch: '/Switch' - */ - if (rtb_Saturation > rtDW->Vq_max_M1) { - /* SignalConversion: '/Signal Conversion2' */ - rtDW->Merge = rtDW->Vq_max_M1; - } else if (rtb_Saturation < rtDW->Gain5) { - /* Switch: '/Switch' incorporates: - * SignalConversion: '/Signal Conversion2' + if (UnitDelay3 != rtb_Sum2_h) { + /* SystemReset for IfAction SubSystem: '/Voltage_Mode_Protection' incorporates: + * ActionPort: '/Action Port' */ - rtDW->Merge = rtDW->Gain5; - } else { - /* SignalConversion: '/Signal Conversion2' incorporates: - * Switch: '/Switch' - */ - rtDW->Merge = rtb_Saturation; + + /* SystemReset for Atomic SubSystem: '/I_backCalc_fixdt' */ + + /* SystemReset for SwitchCase: '/Switch Case' */ + I_backCalc_fixdt_Reset(&rtDW->I_backCalc_fixdt_i, 65536000); + + /* End of SystemReset for SubSystem: '/I_backCalc_fixdt' */ + + /* SystemReset for Atomic SubSystem: '/I_backCalc_fixdt1' */ + I_backCalc_fixdt_Reset(&rtDW->I_backCalc_fixdt1, 65536000); + + /* End of SystemReset for SubSystem: '/I_backCalc_fixdt1' */ + + /* End of SystemReset for SubSystem: '/Voltage_Mode_Protection' */ } - /* End of Switch: '/Switch2' */ - /* End of Outputs for SubSystem: '/Voltage_Mode' */ + /* Outputs for IfAction SubSystem: '/Voltage_Mode_Protection' incorporates: + * ActionPort: '/Action Port' + */ + + /* Outputs for Atomic SubSystem: '/I_backCalc_fixdt' */ + I_backCalc_fixdt((int16_T)(rtDW->Divide1_n - rtDW->Abs5_h), + rtP->cf_iqKiLimProt, rtP->cf_KbLimProt, rtDW->Abs1, 0, + &rtDW->Switch2_a, &rtDW->I_backCalc_fixdt_i); + + /* End of Outputs for SubSystem: '/I_backCalc_fixdt' */ + + /* Outputs for Atomic SubSystem: '/I_backCalc_fixdt1' */ + I_backCalc_fixdt((int16_T)(rtP->n_max - Abs5), rtP->cf_nKiLimProt, + rtP->cf_KbLimProt, rtDW->Abs1, 0, &rtDW->Switch2_o, + &rtDW->I_backCalc_fixdt1); + + /* End of Outputs for SubSystem: '/I_backCalc_fixdt1' */ + + /* End of Outputs for SubSystem: '/Voltage_Mode_Protection' */ break; case 1: - if (UnitDelay3 != rtb_Sum2_h) { - /* SystemReset for IfAction SubSystem: '/Speed_Mode' incorporates: - * ActionPort: '/Action Port' - */ - - /* SystemReset for Atomic SubSystem: '/PI_clamp_fixdt' */ - - /* SystemReset for SwitchCase: '/Switch Case' */ - PI_clamp_fixdt_g_Reset(&rtDW->PI_clamp_fixdt_oc); - - /* End of SystemReset for SubSystem: '/PI_clamp_fixdt' */ - - /* End of SystemReset for SubSystem: '/Speed_Mode' */ - } - - /* Outputs for IfAction SubSystem: '/Speed_Mode' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/Speed_Mode_Protection' incorporates: + * ActionPort: '/Action Port' */ - /* DataTypeConversion: '/Data Type Conversion2' incorporates: - * Constant: '/n_cruiseMotTgt' + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' */ - rtb_Saturation = (int16_T)(rtP->n_cruiseMotTgt << 4); - - /* Switch: '/Switch4' incorporates: - * Constant: '/b_cruiseCtrlEna' - * Logic: '/Logical Operator1' - * RelationalOperator: '/Relational Operator3' - */ - if (rtP->b_cruiseCtrlEna && (rtb_Saturation != 0)) { - /* Switch: '/Switch3' incorporates: - * MinMax: '/MinMax4' - */ - if (rtb_Saturation > 0) { - rtb_TmpSignalConversionAtLow_Pa[0] = rtDW->Vq_max_M1; - - /* MinMax: '/MinMax3' */ - if (rtDW->Merge1 > rtDW->Gain5) { - rtb_TmpSignalConversionAtLow_Pa[1] = rtDW->Merge1; - } else { - rtb_TmpSignalConversionAtLow_Pa[1] = rtDW->Gain5; - } - - /* End of MinMax: '/MinMax3' */ - } else { - if (rtDW->Vq_max_M1 < rtDW->Merge1) { - /* MinMax: '/MinMax4' */ - rtb_TmpSignalConversionAtLow_Pa[0] = rtDW->Vq_max_M1; - } else { - rtb_TmpSignalConversionAtLow_Pa[0] = rtDW->Merge1; - } - - rtb_TmpSignalConversionAtLow_Pa[1] = rtDW->Gain5; - } - - /* End of Switch: '/Switch3' */ + if (rtDW->DataTypeConversion[0] > rtDW->Divide1_n) { + rtb_Saturation1 = rtDW->Divide1_n; + } else if (rtDW->DataTypeConversion[0] < rtDW->Gain1) { + /* Switch: '/Switch' */ + rtb_Saturation1 = rtDW->Gain1; } else { - rtb_TmpSignalConversionAtLow_Pa[0] = rtDW->Vq_max_M1; - rtb_TmpSignalConversionAtLow_Pa[1] = rtDW->Gain5; + rtb_Saturation1 = rtDW->DataTypeConversion[0]; } - /* End of Switch: '/Switch4' */ + /* End of Switch: '/Switch2' */ - /* Switch: '/Switch2' incorporates: - * Constant: '/b_cruiseCtrlEna' + /* Product: '/Divide1' incorporates: + * Constant: '/cf_iqKiLimProt' + * Sum: '/Sum3' */ - if (!rtP->b_cruiseCtrlEna) { - rtb_Saturation = rtDW->Merge1; - } + rtDW->Divide1 = (int16_T)(rtb_Saturation1 - rtDW->DataTypeConversion[0]) + * rtP->cf_iqKiLimProt; - /* End of Switch: '/Switch2' */ - - /* Sum: '/Sum3' */ - rtb_Gain3 = rtb_Saturation - rtb_Switch2_k; - if (rtb_Gain3 > 32767) { - rtb_Gain3 = 32767; - } else { - if (rtb_Gain3 < -32768) { - rtb_Gain3 = -32768; - } - } - - /* Outputs for Atomic SubSystem: '/PI_clamp_fixdt' */ - rtDW->Merge = (int16_T) PI_clamp_fixdt_o((int16_T)rtb_Gain3, rtP->cf_nKp, - rtP->cf_nKi, rtDW->UnitDelay4_DSTATE_eu, - rtb_TmpSignalConversionAtLow_Pa[0], rtb_TmpSignalConversionAtLow_Pa[1], - rtDW->Divide1, &rtDW->PI_clamp_fixdt_oc); - - /* End of Outputs for SubSystem: '/PI_clamp_fixdt' */ - - /* End of Outputs for SubSystem: '/Speed_Mode' */ + /* End of Outputs for SubSystem: '/Speed_Mode_Protection' */ break; case 2: if (UnitDelay3 != rtb_Sum2_h) { - /* SystemReset for IfAction SubSystem: '/Torque_Mode' incorporates: - * ActionPort: '/Action Port' + /* SystemReset for IfAction SubSystem: '/Torque_Mode_Protection' incorporates: + * ActionPort: '/Action Port' */ - /* SystemReset for Atomic SubSystem: '/PI_clamp_fixdt' */ + /* SystemReset for Atomic SubSystem: '/I_backCalc_fixdt' */ - /* SystemReset for SwitchCase: '/Switch Case' */ - PI_clamp_fixdt_b_Reset(&rtDW->PI_clamp_fixdt_at); + /* SystemReset for SwitchCase: '/Switch Case' */ + I_backCalc_fixdt_Reset(&rtDW->I_backCalc_fixdt_j, 58982400); - /* End of SystemReset for SubSystem: '/PI_clamp_fixdt' */ + /* End of SystemReset for SubSystem: '/I_backCalc_fixdt' */ - /* End of SystemReset for SubSystem: '/Torque_Mode' */ + /* End of SystemReset for SubSystem: '/Torque_Mode_Protection' */ } - /* Outputs for IfAction SubSystem: '/Torque_Mode' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/Torque_Mode_Protection' incorporates: + * ActionPort: '/Action Port' */ - /* Gain: '/Gain4' */ - rtb_Saturation = (int16_T)-rtDW->Switch2; - /* Switch: '/Switch2' incorporates: - * RelationalOperator: '/LowerRelop1' - * RelationalOperator: '/UpperRelop' - * Switch: '/Switch' - */ - if (rtDW->Merge1 > rtDW->Divide1_a) { - rtb_Merge_f_idx_2 = rtDW->Divide1_a; - } else if (rtDW->Merge1 < rtDW->Gain1) { - /* Switch: '/Switch' */ - rtb_Merge_f_idx_2 = rtDW->Gain1; - } else { - rtb_Merge_f_idx_2 = rtDW->Merge1; - } + /* Outputs for Atomic SubSystem: '/I_backCalc_fixdt' */ + I_backCalc_fixdt((int16_T)(rtP->n_max - Abs5), rtP->cf_nKiLimProt, + rtP->cf_KbLimProt, rtDW->Vq_max_M1, 0, &rtDW->Switch2_i, + &rtDW->I_backCalc_fixdt_j); - /* End of Switch: '/Switch2' */ + /* End of Outputs for SubSystem: '/I_backCalc_fixdt' */ - /* Sum: '/Sum2' */ - rtb_Gain3 = rtb_Merge_f_idx_2 - rtDW->DataTypeConversion[0]; - if (rtb_Gain3 > 32767) { - rtb_Gain3 = 32767; - } else { - if (rtb_Gain3 < -32768) { - rtb_Gain3 = -32768; - } - } - - /* MinMax: '/MinMax1' */ - if (rtDW->Vq_max_M1 < rtDW->Switch2) { - rtb_Merge_f_idx_2 = rtDW->Vq_max_M1; - } else { - rtb_Merge_f_idx_2 = rtDW->Switch2; - } - - /* End of MinMax: '/MinMax1' */ - - /* MinMax: '/MinMax2' */ - if (!(rtb_Saturation > rtDW->Gain5)) { - rtb_Saturation = rtDW->Gain5; - } - - /* End of MinMax: '/MinMax2' */ - - /* Outputs for Atomic SubSystem: '/PI_clamp_fixdt' */ - rtDW->Merge = (int16_T) PI_clamp_fixdt_a((int16_T)rtb_Gain3, - rtP->cf_iqKp, rtP->cf_iqKi, rtDW->UnitDelay4_DSTATE_eu, - rtb_Merge_f_idx_2, rtb_Saturation, 0, &rtDW->PI_clamp_fixdt_at); - - /* End of Outputs for SubSystem: '/PI_clamp_fixdt' */ - - /* End of Outputs for SubSystem: '/Torque_Mode' */ - break; - - case 3: - /* Outputs for IfAction SubSystem: '/Open_Mode' incorporates: - * ActionPort: '/Action Port' - */ - rtDW->Merge = rtDW->Merge1; - - /* End of Outputs for SubSystem: '/Open_Mode' */ + /* End of Outputs for SubSystem: '/Torque_Mode_Protection' */ break; } - /* End of SwitchCase: '/Switch Case' */ - /* End of Outputs for SubSystem: '/FOC' */ + /* End of SwitchCase: '/Switch Case' */ + + /* Gain: '/Gain4' */ + rtDW->Gain4 = (int16_T)-rtDW->i_max; + + /* End of Outputs for SubSystem: '/Motor_Limitations_Enabled' */ } - /* End of If: '/If1' */ + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Motor_Limitations' */ + } else { + if (rtDW->UnitDelay6_DSTATE) { + /* Outputs for Function Call SubSystem: '/FOC' */ + /* If: '/If1' incorporates: + * Constant: '/z_ctrlTypSel' + */ + rtb_Sum2_h = rtDW->If1_ActiveSubsystem_j; + UnitDelay3 = -1; + if (rtP->z_ctrlTypSel == 2) { + UnitDelay3 = 0; + } - /* Sum: '/Sum6' incorporates: - * Interpolation_n-D: '/r_cos_M1' - * Interpolation_n-D: '/r_sin_M1' - * Product: '/Divide1' - * Product: '/Divide4' + rtDW->If1_ActiveSubsystem_j = UnitDelay3; + if ((rtb_Sum2_h != UnitDelay3) && (rtb_Sum2_h == 0)) { + /* Disable for SwitchCase: '/Switch Case' */ + rtDW->SwitchCase_ActiveSubsystem = -1; + + /* Disable for If: '/If1' */ + rtDW->If1_ActiveSubsystem_a = -1; + } + + if (UnitDelay3 == 0) { + /* Outputs for IfAction SubSystem: '/FOC_Enabled' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * Constant: '/cf_nKi' + * Constant: '/cf_nKp' + * Inport: '/r_inpTgtSca' + * Sum: '/Sum3' + * UnitDelay: '/UnitDelay4' + */ + rtb_Sum2_h = rtDW->SwitchCase_ActiveSubsystem; + switch (rtDW->z_ctrlMod) { + case 1: + break; + + case 2: + UnitDelay3 = 1; + break; + + case 3: + UnitDelay3 = 2; + break; + + default: + UnitDelay3 = 3; + break; + } + + rtDW->SwitchCase_ActiveSubsystem = UnitDelay3; + switch (UnitDelay3) { + case 0: + /* Outputs for IfAction SubSystem: '/Voltage_Mode' incorporates: + * ActionPort: '/Action Port' + */ + /* MinMax: '/MinMax' */ + if (rtDW->Abs1 < rtDW->Switch2_a) { + DataTypeConversion2 = rtDW->Abs1; + } else { + DataTypeConversion2 = rtDW->Switch2_a; + } + + if (!(DataTypeConversion2 < rtDW->Switch2_o)) { + DataTypeConversion2 = rtDW->Switch2_o; + } + + /* End of MinMax: '/MinMax' */ + + /* Signum: '/SignDeltaU2' */ + if (rtDW->Merge1 < 0) { + rtb_Saturation1 = -1; + } else { + rtb_Saturation1 = (int16_T)(rtDW->Merge1 > 0); + } + + /* End of Signum: '/SignDeltaU2' */ + + /* Product: '/Divide1' */ + rtb_Saturation = (int16_T)(DataTypeConversion2 * rtb_Saturation1); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_Saturation > rtDW->Vq_max_M1) { + /* SignalConversion: '/Signal Conversion2' */ + rtDW->Merge = rtDW->Vq_max_M1; + } else if (rtb_Saturation < rtDW->Gain5) { + /* Switch: '/Switch' incorporates: + * SignalConversion: '/Signal Conversion2' + */ + rtDW->Merge = rtDW->Gain5; + } else { + /* SignalConversion: '/Signal Conversion2' incorporates: + * Switch: '/Switch' + */ + rtDW->Merge = rtb_Saturation; + } + + /* End of Switch: '/Switch2' */ + /* End of Outputs for SubSystem: '/Voltage_Mode' */ + break; + + case 1: + if (UnitDelay3 != rtb_Sum2_h) { + /* SystemReset for IfAction SubSystem: '/Speed_Mode' incorporates: + * ActionPort: '/Action Port' + */ + + /* SystemReset for Atomic SubSystem: '/PI_clamp_fixdt' */ + + /* SystemReset for SwitchCase: '/Switch Case' */ + PI_clamp_fixdt_b_Reset(&rtDW->PI_clamp_fixdt_l4); + + /* End of SystemReset for SubSystem: '/PI_clamp_fixdt' */ + + /* End of SystemReset for SubSystem: '/Speed_Mode' */ + } + + /* Outputs for IfAction SubSystem: '/Speed_Mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * Constant: '/n_cruiseMotTgt' + */ + rtb_Saturation = (int16_T)(rtP->n_cruiseMotTgt << 4); + + /* Switch: '/Switch4' incorporates: + * Constant: '/b_cruiseCtrlEna' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator3' + */ + if (rtP->b_cruiseCtrlEna && (rtb_Saturation != 0)) { + /* Switch: '/Switch3' incorporates: + * MinMax: '/MinMax4' + */ + if (rtb_Saturation > 0) { + rtb_TmpSignalConversionAtLow_Pa[0] = rtDW->Vq_max_M1; + + /* MinMax: '/MinMax3' */ + if (rtDW->Merge1 > rtDW->Gain5) { + rtb_TmpSignalConversionAtLow_Pa[1] = rtDW->Merge1; + } else { + rtb_TmpSignalConversionAtLow_Pa[1] = rtDW->Gain5; + } + + /* End of MinMax: '/MinMax3' */ + } else { + if (rtDW->Vq_max_M1 < rtDW->Merge1) { + /* MinMax: '/MinMax4' */ + rtb_TmpSignalConversionAtLow_Pa[0] = rtDW->Vq_max_M1; + } else { + rtb_TmpSignalConversionAtLow_Pa[0] = rtDW->Merge1; + } + + rtb_TmpSignalConversionAtLow_Pa[1] = rtDW->Gain5; + } + + /* End of Switch: '/Switch3' */ + } else { + rtb_TmpSignalConversionAtLow_Pa[0] = rtDW->Vq_max_M1; + rtb_TmpSignalConversionAtLow_Pa[1] = rtDW->Gain5; + } + + /* End of Switch: '/Switch4' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/b_cruiseCtrlEna' + */ + if (!rtP->b_cruiseCtrlEna) { + rtb_Saturation = rtDW->Merge1; + } + + /* End of Switch: '/Switch2' */ + + /* Sum: '/Sum3' */ + rtb_Gain3 = rtb_Saturation - Switch2; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; + } else { + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; + } + } + + /* Outputs for Atomic SubSystem: '/PI_clamp_fixdt' */ + PI_clamp_fixdt_l((int16_T)rtb_Gain3, rtP->cf_nKp, rtP->cf_nKi, + rtDW->UnitDelay4_DSTATE_eu, + rtb_TmpSignalConversionAtLow_Pa[0], + rtb_TmpSignalConversionAtLow_Pa[1], rtDW->Divide1, + &rtDW->Merge, &rtDW->PI_clamp_fixdt_l4); + + /* End of Outputs for SubSystem: '/PI_clamp_fixdt' */ + + /* End of Outputs for SubSystem: '/Speed_Mode' */ + break; + + case 2: + if (UnitDelay3 != rtb_Sum2_h) { + /* SystemReset for IfAction SubSystem: '/Torque_Mode' incorporates: + * ActionPort: '/Action Port' + */ + + /* SystemReset for Atomic SubSystem: '/PI_clamp_fixdt' */ + + /* SystemReset for SwitchCase: '/Switch Case' */ + PI_clamp_fixdt_g_Reset(&rtDW->PI_clamp_fixdt_kh); + + /* End of SystemReset for SubSystem: '/PI_clamp_fixdt' */ + + /* End of SystemReset for SubSystem: '/Torque_Mode' */ + } + + /* Outputs for IfAction SubSystem: '/Torque_Mode' incorporates: + * ActionPort: '/Action Port' + */ + /* Gain: '/Gain4' */ + rtb_Saturation = (int16_T)-rtDW->Switch2_i; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtDW->Merge1 > rtDW->Divide1_n) { + rtb_Saturation1 = rtDW->Divide1_n; + } else if (rtDW->Merge1 < rtDW->Gain1) { + /* Switch: '/Switch' */ + rtb_Saturation1 = rtDW->Gain1; + } else { + rtb_Saturation1 = rtDW->Merge1; + } + + /* End of Switch: '/Switch2' */ + + /* Sum: '/Sum2' */ + rtb_Gain3 = rtb_Saturation1 - rtDW->DataTypeConversion[0]; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; + } else { + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; + } + } + + /* MinMax: '/MinMax1' */ + if (rtDW->Vq_max_M1 < rtDW->Switch2_i) { + rtb_Saturation1 = rtDW->Vq_max_M1; + } else { + rtb_Saturation1 = rtDW->Switch2_i; + } + + /* End of MinMax: '/MinMax1' */ + + /* MinMax: '/MinMax2' */ + if (!(rtb_Saturation > rtDW->Gain5)) { + rtb_Saturation = rtDW->Gain5; + } + + /* End of MinMax: '/MinMax2' */ + + /* Outputs for Atomic SubSystem: '/PI_clamp_fixdt' */ + + /* SignalConversion: '/Signal Conversion2' incorporates: + * Constant: '/cf_iqKi' + * Constant: '/cf_iqKp' + * Constant: '/constant2' + * Sum: '/Sum2' + * UnitDelay: '/UnitDelay4' + */ + PI_clamp_fixdt_k((int16_T)rtb_Gain3, rtP->cf_iqKp, rtP->cf_iqKi, + rtDW->UnitDelay4_DSTATE_eu, rtb_Saturation1, + rtb_Saturation, 0, &rtDW->Merge, + &rtDW->PI_clamp_fixdt_kh); + + /* End of Outputs for SubSystem: '/PI_clamp_fixdt' */ + + /* End of Outputs for SubSystem: '/Torque_Mode' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Open_Mode' incorporates: + * ActionPort: '/Action Port' + */ + rtDW->Merge = rtDW->Merge1; + + /* End of Outputs for SubSystem: '/Open_Mode' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* If: '/If1' incorporates: + * Constant: '/cf_idKi1' + * Constant: '/cf_idKp1' + * Constant: '/constant1' + * Constant: '/constant2' + * Sum: '/Sum3' + */ + rtb_Sum2_h = rtDW->If1_ActiveSubsystem_a; + UnitDelay3 = -1; + if (rtb_LogicalOperator) { + UnitDelay3 = 0; + } + + rtDW->If1_ActiveSubsystem_a = UnitDelay3; + if (UnitDelay3 == 0) { + if (0 != rtb_Sum2_h) { + /* SystemReset for IfAction SubSystem: '/Vd_Calculation' incorporates: + * ActionPort: '/Action Port' + */ + + /* SystemReset for Atomic SubSystem: '/PI_clamp_fixdt' */ + + /* SystemReset for If: '/If1' */ + PI_clamp_fixdt_Reset(&rtDW->PI_clamp_fixdt_i); + + /* End of SystemReset for SubSystem: '/PI_clamp_fixdt' */ + + /* End of SystemReset for SubSystem: '/Vd_Calculation' */ + } + + /* Outputs for IfAction SubSystem: '/Vd_Calculation' incorporates: + * ActionPort: '/Action Port' + */ + /* Gain: '/toNegative' */ + rtb_Saturation = (int16_T)-rtDW->Divide3; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_Saturation > rtDW->i_max) { + rtb_Saturation = rtDW->i_max; + } else { + if (rtb_Saturation < rtDW->Gain4) { + /* Switch: '/Switch' */ + rtb_Saturation = rtDW->Gain4; + } + } + + /* End of Switch: '/Switch2' */ + + /* Sum: '/Sum3' */ + rtb_Gain3 = rtb_Saturation - rtDW->DataTypeConversion[1]; + if (rtb_Gain3 > 32767) { + rtb_Gain3 = 32767; + } else { + if (rtb_Gain3 < -32768) { + rtb_Gain3 = -32768; + } + } + + /* Outputs for Atomic SubSystem: '/PI_clamp_fixdt' */ + PI_clamp_fixdt((int16_T)rtb_Gain3, rtP->cf_idKp, rtP->cf_idKi, 0, + rtDW->Vd_max1, rtDW->Gain3, 0, &rtDW->Switch1, + &rtDW->PI_clamp_fixdt_i); + + /* End of Outputs for SubSystem: '/PI_clamp_fixdt' */ + + /* End of Outputs for SubSystem: '/Vd_Calculation' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/FOC_Enabled' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/FOC' */ + } + } + + /* End of Chart: '/Task_Scheduler' */ + + /* If: '/If2' incorporates: + * Constant: '/z_ctrlTypSel' + * Constant: '/CTRL_COMM1' + * RelationalOperator: '/Relational Operator6' + * Switch: '/Switch2' + */ + rtb_Sum2_h = rtDW->If2_ActiveSubsystem; + UnitDelay3 = -1; + if (rtP->z_ctrlTypSel == 2) { + rtb_Saturation = rtDW->Merge; + UnitDelay3 = 0; + } else { + rtb_Saturation = rtDW->Merge1; + } + + rtDW->If2_ActiveSubsystem = UnitDelay3; + if ((rtb_Sum2_h != UnitDelay3) && (rtb_Sum2_h == 0)) { + /* Disable for Outport: '/V_phaABC_FOC' */ + rtDW->Gain4_e[0] = 0; + rtDW->Gain4_e[1] = 0; + rtDW->Gain4_e[2] = 0; + } + + if (UnitDelay3 == 0) { + /* Outputs for IfAction SubSystem: '/Clarke_Park_Transform_Inverse' incorporates: + * ActionPort: '/Action Port' */ - rtb_Gain3 = (int16_T)((rtDW->Switch1 * rtConstP.r_cos_M1_Table[rtb_Sum_l]) >> - 14) - (int16_T)((rtDW->Merge * - rtConstP.r_sin_M1_Table[rtb_Sum_l]) >> 14); + /* Sum: '/Sum6' incorporates: + * Product: '/Divide1' + * Product: '/Divide4' + */ + rtb_Gain3 = (int16_T)((rtDW->Switch1 * rtDW->r_cos_M1) >> 14) - (int16_T) + ((rtDW->Merge * rtDW->r_sin_M1) >> 14); if (rtb_Gain3 > 32767) { rtb_Gain3 = 32767; } else { @@ -2686,49 +2817,45 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - /* Sum: '/Sum1' incorporates: - * Interpolation_n-D: '/r_cos_M1' - * Interpolation_n-D: '/r_sin_M1' - * Product: '/Divide2' - * Product: '/Divide3' + /* Sum: '/Sum1' incorporates: + * Product: '/Divide2' + * Product: '/Divide3' */ - rtb_DataTypeConversion = (int16_T)((rtDW->Switch1 * - rtConstP.r_sin_M1_Table[rtb_Sum_l]) >> 14) + (int16_T)((rtDW->Merge * - rtConstP.r_cos_M1_Table[rtb_Sum_l]) >> 14); - if (rtb_DataTypeConversion > 32767) { - rtb_DataTypeConversion = 32767; + rtb_Sum1_jt = (int16_T)((rtDW->Switch1 * rtDW->r_sin_M1) >> 14) + (int16_T) + ((rtDW->Merge * rtDW->r_cos_M1) >> 14); + if (rtb_Sum1_jt > 32767) { + rtb_Sum1_jt = 32767; } else { - if (rtb_DataTypeConversion < -32768) { - rtb_DataTypeConversion = -32768; + if (rtb_Sum1_jt < -32768) { + rtb_Sum1_jt = -32768; } } - /* Gain: '/Gain1' incorporates: - * Sum: '/Sum1' + /* Gain: '/Gain1' incorporates: + * Sum: '/Sum1' */ - rtb_DataTypeConversion *= 14189; + rtb_Sum1_jt *= 14189; - /* Sum: '/Sum6' incorporates: - * Gain: '/Gain1' - * Gain: '/Gain3' - * Sum: '/Sum6' + /* Sum: '/Sum6' incorporates: + * Gain: '/Gain1' + * Gain: '/Gain3' + * Sum: '/Sum6' */ - rtb_DataTypeConversion = (((rtb_DataTypeConversion < 0 ? 16383 : 0) + - rtb_DataTypeConversion) >> 14) - ((int16_T)(((int16_T)rtb_Gain3 < 0) + - (int16_T)rtb_Gain3) >> 1); - if (rtb_DataTypeConversion > 32767) { - rtb_DataTypeConversion = 32767; + rtb_Sum1_jt = (((rtb_Sum1_jt < 0 ? 16383 : 0) + rtb_Sum1_jt) >> 14) - + ((int16_T)(((int16_T)rtb_Gain3 < 0) + (int16_T)rtb_Gain3) >> 1); + if (rtb_Sum1_jt > 32767) { + rtb_Sum1_jt = 32767; } else { - if (rtb_DataTypeConversion < -32768) { - rtb_DataTypeConversion = -32768; + if (rtb_Sum1_jt < -32768) { + rtb_Sum1_jt = -32768; } } - /* Sum: '/Sum2' incorporates: - * Sum: '/Sum6' - * Sum: '/Sum6' + /* Sum: '/Sum2' incorporates: + * Sum: '/Sum6' + * Sum: '/Sum6' */ - rtb_Switch1 = -(int16_T)rtb_Gain3 - (int16_T)rtb_DataTypeConversion; + rtb_Switch1 = -(int16_T)rtb_Gain3 - (int16_T)rtb_Sum1_jt; if (rtb_Switch1 > 32767) { rtb_Switch1 = 32767; } else { @@ -2737,39 +2864,39 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - /* MinMax: '/MinMax1' incorporates: - * Sum: '/Sum2' - * Sum: '/Sum6' - * Sum: '/Sum6' + /* MinMax: '/MinMax1' incorporates: + * Sum: '/Sum2' + * Sum: '/Sum6' + * Sum: '/Sum6' */ - rtb_Switch2_l = (int16_T)rtb_Gain3; - if (!((int16_T)rtb_Gain3 < (int16_T)rtb_DataTypeConversion)) { - rtb_Switch2_l = (int16_T)rtb_DataTypeConversion; + DataTypeConversion2 = (int16_T)rtb_Gain3; + if (!((int16_T)rtb_Gain3 < (int16_T)rtb_Sum1_jt)) { + DataTypeConversion2 = (int16_T)rtb_Sum1_jt; } - if (!(rtb_Switch2_l < (int16_T)rtb_Switch1)) { - rtb_Switch2_l = (int16_T)rtb_Switch1; + if (!(DataTypeConversion2 < (int16_T)rtb_Switch1)) { + DataTypeConversion2 = (int16_T)rtb_Switch1; } - /* MinMax: '/MinMax2' incorporates: - * Sum: '/Sum2' - * Sum: '/Sum6' - * Sum: '/Sum6' + /* MinMax: '/MinMax2' incorporates: + * Sum: '/Sum2' + * Sum: '/Sum6' + * Sum: '/Sum6' */ - rtb_Saturation = (int16_T)rtb_Gain3; - if (!((int16_T)rtb_Gain3 > (int16_T)rtb_DataTypeConversion)) { - rtb_Saturation = (int16_T)rtb_DataTypeConversion; + rtb_Saturation1 = (int16_T)rtb_Gain3; + if (!((int16_T)rtb_Gain3 > (int16_T)rtb_Sum1_jt)) { + rtb_Saturation1 = (int16_T)rtb_Sum1_jt; } - if (!(rtb_Saturation > (int16_T)rtb_Switch1)) { - rtb_Saturation = (int16_T)rtb_Switch1; + if (!(rtb_Saturation1 > (int16_T)rtb_Switch1)) { + rtb_Saturation1 = (int16_T)rtb_Switch1; } - /* Sum: '/Add' incorporates: - * MinMax: '/MinMax1' - * MinMax: '/MinMax2' + /* Sum: '/Add' incorporates: + * MinMax: '/MinMax1' + * MinMax: '/MinMax2' */ - rtb_Sum1 = rtb_Switch2_l + rtb_Saturation; + rtb_Sum1 = DataTypeConversion2 + rtb_Saturation1; if (rtb_Sum1 > 32767) { rtb_Sum1 = 32767; } else { @@ -2778,15 +2905,15 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - /* Gain: '/Gain2' incorporates: - * Sum: '/Add' + /* Gain: '/Gain2' incorporates: + * Sum: '/Add' */ - rtb_DataTypeConversion2 = (int16_T)(rtb_Sum1 >> 1); + rtb_Merge1 = (int16_T)(rtb_Sum1 >> 1); - /* Sum: '/Add1' incorporates: - * Sum: '/Sum6' + /* Sum: '/Add1' incorporates: + * Sum: '/Sum6' */ - rtb_Gain3 = (int16_T)rtb_Gain3 - rtb_DataTypeConversion2; + rtb_Gain3 = (int16_T)rtb_Gain3 - rtb_Merge1; if (rtb_Gain3 > 32767) { rtb_Gain3 = 32767; } else { @@ -2795,15 +2922,15 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - /* Gain: '/Gain4' incorporates: - * Sum: '/Add1' + /* Gain: '/Gain4' incorporates: + * Sum: '/Add1' */ - rtDW->Gain4[0] = (int16_T)((18919 * rtb_Gain3) >> 14); + rtDW->Gain4_e[0] = (int16_T)((18919 * rtb_Gain3) >> 14); - /* Sum: '/Add1' incorporates: - * Sum: '/Sum6' + /* Sum: '/Add1' incorporates: + * Sum: '/Sum6' */ - rtb_Gain3 = (int16_T)rtb_DataTypeConversion - rtb_DataTypeConversion2; + rtb_Gain3 = (int16_T)rtb_Sum1_jt - rtb_Merge1; if (rtb_Gain3 > 32767) { rtb_Gain3 = 32767; } else { @@ -2812,15 +2939,15 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - /* Gain: '/Gain4' incorporates: - * Sum: '/Add1' + /* Gain: '/Gain4' incorporates: + * Sum: '/Add1' */ - rtDW->Gain4[1] = (int16_T)((18919 * rtb_Gain3) >> 14); + rtDW->Gain4_e[1] = (int16_T)((18919 * rtb_Gain3) >> 14); - /* Sum: '/Add1' incorporates: - * Sum: '/Sum2' + /* Sum: '/Add1' incorporates: + * Sum: '/Sum2' */ - rtb_Gain3 = (int16_T)rtb_Switch1 - rtb_DataTypeConversion2; + rtb_Gain3 = (int16_T)rtb_Switch1 - rtb_Merge1; if (rtb_Gain3 > 32767) { rtb_Gain3 = 32767; } else { @@ -2829,212 +2956,196 @@ void BLDC_controller_step(RT_MODEL *const rtM) } } - /* Gain: '/Gain4' incorporates: - * Sum: '/Add1' + /* Gain: '/Gain4' incorporates: + * Sum: '/Add1' */ - rtDW->Gain4[2] = (int16_T)((18919 * rtb_Gain3) >> 14); + rtDW->Gain4_e[2] = (int16_T)((18919 * rtb_Gain3) >> 14); - /* Update for UnitDelay: '/UnitDelay4' */ - rtDW->UnitDelay4_DSTATE_h = rtDW->Switch1; - - /* End of Outputs for SubSystem: '/F05_Field_Oriented_Control' */ + /* End of Outputs for SubSystem: '/Clarke_Park_Transform_Inverse' */ } - /* End of If: '/If1' */ + /* End of If: '/If2' */ - /* Switch: '/Switch2' incorporates: + /* If: '/If' incorporates: + * Constant: '/vec_hallToPos' * Constant: '/z_ctrlTypSel' - * Constant: '/CTRL_COMM1' - * RelationalOperator: '/Relational Operator6' - */ - if (rtP->z_ctrlTypSel == 2) { - rtb_Saturation = rtDW->Merge; - } else { - rtb_Saturation = rtDW->Merge1; - } - - /* End of Switch: '/Switch2' */ - - /* If: '/If' incorporates: - * Constant: '/vec_hallToPos' - * Constant: '/z_ctrlTypSel' - * Constant: '/CTRL_COMM2' - * Constant: '/CTRL_COMM3' - * Inport: '/V_phaABC_FOC_in' - * Logic: '/Logical Operator1' - * Logic: '/Logical Operator2' - * LookupNDDirect: '/z_commutMap_M1' - * RelationalOperator: '/Relational Operator1' - * RelationalOperator: '/Relational Operator2' - * Selector: '/Selector' + * Constant: '/CTRL_COMM2' + * Constant: '/CTRL_COMM3' + * Inport: '/V_phaABC_FOC_in' + * Logic: '/Logical Operator1' + * Logic: '/Logical Operator2' + * LookupNDDirect: '/z_commutMap_M1' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * Selector: '/Selector' * - * About '/z_commutMap_M1': + * About '/z_commutMap_M1': * 2-dimensional Direct Look-Up returning a Column */ if (rtb_LogicalOperator && (rtP->z_ctrlTypSel == 2)) { - /* Outputs for IfAction SubSystem: '/FOC_Method' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/FOC_Method' incorporates: + * ActionPort: '/Action Port' */ - rtb_DataTypeConversion2 = rtDW->Gain4[0]; - rtb_Saturation1 = rtDW->Gain4[1]; - rtb_Merge_f_idx_2 = rtDW->Gain4[2]; + DataTypeConversion2 = rtDW->Gain4_e[0]; + rtb_Saturation1 = rtDW->Gain4_e[1]; + rtb_Merge1 = rtDW->Gain4_e[2]; - /* End of Outputs for SubSystem: '/FOC_Method' */ + /* End of Outputs for SubSystem: '/FOC_Method' */ } else if (rtb_LogicalOperator && (rtP->z_ctrlTypSel == 1)) { - /* Outputs for IfAction SubSystem: '/SIN_Method' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/SIN_Method' incorporates: + * ActionPort: '/Action Port' */ - /* Switch: '/Switch_PhaAdv' incorporates: - * Constant: '/b_fieldWeakEna' - * Product: '/Divide2' - * Product: '/Divide3' - * Sum: '/Sum3' + /* Switch: '/Switch_PhaAdv' incorporates: + * Constant: '/b_fieldWeakEna' + * Product: '/Divide2' + * Product: '/Divide3' + * Sum: '/Sum3' */ if (rtP->b_fieldWeakEna) { - /* Sum: '/Sum3' incorporates: - * Product: '/Product2' + /* Sum: '/Sum3' incorporates: + * Product: '/Product2' */ - rtb_Saturation1 = (int16_T)((int16_T)((int16_T)(rtDW->Divide3 * - rtDW->Switch2_e) << 2) + rtb_Merge); - rtb_Saturation1 -= (int16_T)((int16_T)((int16_T)div_nde_s32_floor - (rtb_Saturation1, 23040) * 360) << 6); + DataTypeConversion2 = (int16_T)((int16_T)((int16_T)(rtDW->Divide3 * + rtDW->Switch2_e) << 2) + rtb_Merge_m); + DataTypeConversion2 -= (int16_T)((int16_T)((int16_T)div_nde_s32_floor + (DataTypeConversion2, 23040) * 360) << 6); } else { - rtb_Saturation1 = rtb_Merge; + DataTypeConversion2 = rtb_Merge_m; } - /* End of Switch: '/Switch_PhaAdv' */ + /* End of Switch: '/Switch_PhaAdv' */ - /* PreLookup: '/a_elecAngle_XA' */ - rtb_Sum = plook_u8s16_evencka(rtb_Saturation1, 0, 128U, 180U); + /* PreLookup: '/a_elecAngle_XA' */ + Sum = plook_u8s16_evencka(DataTypeConversion2, 0, 128U, 180U); - /* Product: '/Divide2' incorporates: - * Interpolation_n-D: '/r_sin3PhaA_M1' - * Interpolation_n-D: '/r_sin3PhaB_M1' - * Interpolation_n-D: '/r_sin3PhaC_M1' + /* Product: '/Divide2' incorporates: + * Interpolation_n-D: '/r_sin3PhaA_M1' + * Interpolation_n-D: '/r_sin3PhaB_M1' + * Interpolation_n-D: '/r_sin3PhaC_M1' */ - rtb_DataTypeConversion2 = (int16_T)((rtb_Saturation * - rtConstP.r_sin3PhaA_M1_Table[rtb_Sum]) >> 14); + DataTypeConversion2 = (int16_T)((rtb_Saturation * + rtConstP.r_sin3PhaA_M1_Table[Sum]) >> 14); rtb_Saturation1 = (int16_T)((rtb_Saturation * - rtConstP.r_sin3PhaB_M1_Table[rtb_Sum]) >> 14); - rtb_Merge_f_idx_2 = (int16_T)((rtb_Saturation * - rtConstP.r_sin3PhaC_M1_Table[rtb_Sum]) >> 14); + rtConstP.r_sin3PhaB_M1_Table[Sum]) >> 14); + rtb_Merge1 = (int16_T)((rtb_Saturation * rtConstP.r_sin3PhaC_M1_Table[Sum]) >> + 14); - /* End of Outputs for SubSystem: '/SIN_Method' */ + /* End of Outputs for SubSystem: '/SIN_Method' */ } else { - /* Outputs for IfAction SubSystem: '/COM_Method' incorporates: - * ActionPort: '/Action Port' + /* Outputs for IfAction SubSystem: '/COM_Method' incorporates: + * ActionPort: '/Action Port' */ - if (rtConstP.vec_hallToPos_Value[rtb_Sum] > 5) { - /* LookupNDDirect: '/z_commutMap_M1' + if (rtConstP.vec_hallToPos_Value[Sum] > 5) { + /* LookupNDDirect: '/z_commutMap_M1' * - * About '/z_commutMap_M1': + * About '/z_commutMap_M1': * 2-dimensional Direct Look-Up returning a Column */ rtb_Sum2_h = 5; - } else if (rtConstP.vec_hallToPos_Value[rtb_Sum] < 0) { - /* LookupNDDirect: '/z_commutMap_M1' + } else if (rtConstP.vec_hallToPos_Value[Sum] < 0) { + /* LookupNDDirect: '/z_commutMap_M1' * - * About '/z_commutMap_M1': + * About '/z_commutMap_M1': * 2-dimensional Direct Look-Up returning a Column */ rtb_Sum2_h = 0; } else { - /* LookupNDDirect: '/z_commutMap_M1' incorporates: - * Constant: '/vec_hallToPos' - * Selector: '/Selector' + /* LookupNDDirect: '/z_commutMap_M1' incorporates: + * Constant: '/vec_hallToPos' + * Selector: '/Selector' * - * About '/z_commutMap_M1': + * About '/z_commutMap_M1': * 2-dimensional Direct Look-Up returning a Column */ - rtb_Sum2_h = rtConstP.vec_hallToPos_Value[rtb_Sum]; + rtb_Sum2_h = rtConstP.vec_hallToPos_Value[Sum]; } - /* LookupNDDirect: '/z_commutMap_M1' incorporates: - * Constant: '/vec_hallToPos' - * Selector: '/Selector' + /* LookupNDDirect: '/z_commutMap_M1' incorporates: + * Constant: '/vec_hallToPos' + * Selector: '/Selector' * - * About '/z_commutMap_M1': + * About '/z_commutMap_M1': * 2-dimensional Direct Look-Up returning a Column */ - rtb_DataTypeConversion = rtb_Sum2_h * 3; + rtb_Sum1_jt = rtb_Sum2_h * 3; - /* Product: '/Divide2' incorporates: - * LookupNDDirect: '/z_commutMap_M1' + /* Product: '/Divide2' incorporates: + * LookupNDDirect: '/z_commutMap_M1' * - * About '/z_commutMap_M1': + * About '/z_commutMap_M1': * 2-dimensional Direct Look-Up returning a Column */ - rtb_DataTypeConversion2 = (int16_T)(rtb_Saturation * - rtConstP.z_commutMap_M1_table[rtb_DataTypeConversion]); - rtb_Saturation1 = (int16_T)(rtConstP.z_commutMap_M1_table[1 + - rtb_DataTypeConversion] * rtb_Saturation); - rtb_Merge_f_idx_2 = (int16_T)(rtConstP.z_commutMap_M1_table[2 + - rtb_DataTypeConversion] * rtb_Saturation); + DataTypeConversion2 = (int16_T)(rtb_Saturation * + rtConstP.z_commutMap_M1_table[rtb_Sum1_jt]); + rtb_Saturation1 = (int16_T)(rtConstP.z_commutMap_M1_table[1 + rtb_Sum1_jt] * + rtb_Saturation); + rtb_Merge1 = (int16_T)(rtConstP.z_commutMap_M1_table[2 + rtb_Sum1_jt] * + rtb_Saturation); - /* End of Outputs for SubSystem: '/COM_Method' */ + /* End of Outputs for SubSystem: '/COM_Method' */ } - /* End of If: '/If' */ + /* End of If: '/If' */ /* Outport: '/DC_phaA' incorporates: - * DataTypeConversion: '/Data Type Conversion6' + * DataTypeConversion: '/Data Type Conversion6' */ - rtY->DC_phaA = (int16_T)(rtb_DataTypeConversion2 >> 4); + rtY->DC_phaA = (int16_T)(DataTypeConversion2 >> 4); /* Outport: '/DC_phaB' incorporates: - * DataTypeConversion: '/Data Type Conversion6' + * DataTypeConversion: '/Data Type Conversion6' */ rtY->DC_phaB = (int16_T)(rtb_Saturation1 >> 4); - /* Update for UnitDelay: '/UnitDelay3' incorporates: + /* Update for UnitDelay: '/UnitDelay3' incorporates: * Inport: '/b_hallA ' */ rtDW->UnitDelay3_DSTATE_fy = rtU->b_hallA; - /* Update for UnitDelay: '/UnitDelay1' incorporates: + /* Update for UnitDelay: '/UnitDelay1' incorporates: * Inport: '/b_hallB' */ rtDW->UnitDelay1_DSTATE = rtU->b_hallB; - /* Update for UnitDelay: '/UnitDelay2' incorporates: + /* Update for UnitDelay: '/UnitDelay2' incorporates: * Inport: '/b_hallC' */ rtDW->UnitDelay2_DSTATE_f = rtU->b_hallC; - /* Update for UnitDelay: '/UnitDelay3' */ + /* Update for UnitDelay: '/UnitDelay3' */ rtDW->UnitDelay3_DSTATE = rtb_Switch1_l; - /* Update for UnitDelay: '/UnitDelay4' */ - rtDW->UnitDelay4_DSTATE_e = rtb_Abs5; + /* Update for UnitDelay: '/UnitDelay4' */ + rtDW->UnitDelay4_DSTATE_e = Abs5; - /* Update for UnitDelay: '/UnitDelay2' incorporates: - * UnitDelay: '/UnitDelay6' + /* Update for UnitDelay: '/UnitDelay2' incorporates: + * UnitDelay: '/UnitDelay6' */ - rtDW->UnitDelay2_DSTATE_g = rtDW->UnitDelay6_DSTATE; + rtDW->UnitDelay2_DSTATE_c = rtDW->UnitDelay6_DSTATE; - /* Update for UnitDelay: '/UnitDelay4' */ + /* Update for UnitDelay: '/UnitDelay5' */ + rtDW->UnitDelay5_DSTATE_m = rtb_RelationalOperator4_d; + + /* Update for UnitDelay: '/UnitDelay6' */ + rtDW->UnitDelay6_DSTATE = rtb_UnitDelay5_e; + + /* Update for UnitDelay: '/UnitDelay4' */ rtDW->UnitDelay4_DSTATE_eu = rtb_Saturation; - /* Update for UnitDelay: '/UnitDelay5' */ - rtDW->UnitDelay5_DSTATE_l = rtb_RelationalOperator4_d; - - /* Update for UnitDelay: '/UnitDelay6' */ - rtDW->UnitDelay6_DSTATE = rtb_RelationalOperator1_m; - /* Outport: '/DC_phaC' incorporates: - * DataTypeConversion: '/Data Type Conversion6' + * DataTypeConversion: '/Data Type Conversion6' */ - rtY->DC_phaC = (int16_T)(rtb_Merge_f_idx_2 >> 4); + rtY->DC_phaC = (int16_T)(rtb_Merge1 >> 4); /* Outport: '/n_mot' incorporates: * DataTypeConversion: '/Data Type Conversion1' */ - rtY->n_mot = (int16_T)(rtb_Switch2_k >> 4); + rtY->n_mot = (int16_T)(Switch2 >> 4); /* Outport: '/a_elecAngle' incorporates: * DataTypeConversion: '/Data Type Conversion3' */ - rtY->a_elecAngle = (int16_T)(rtb_Merge >> 6); + rtY->a_elecAngle = (int16_T)(rtb_Merge_m >> 6); /* End of Outputs for SubSystem: '/BLDC_controller' */ @@ -3052,154 +3163,184 @@ void BLDC_controller_initialize(RT_MODEL *const rtM) DW *rtDW = ((DW *) rtM->dwork); /* Start for Atomic SubSystem: '/BLDC_controller' */ - /* Start for If: '/If4' */ - rtDW->If4_ActiveSubsystem = -1; - - /* Start for IfAction SubSystem: '/F03_Control_Mode_Manager' */ - /* Start for If: '/If2' */ - rtDW->If2_ActiveSubsystem = -1; - - /* End of Start for SubSystem: '/F03_Control_Mode_Manager' */ - - /* Start for If: '/If1' */ + /* Start for If: '/If1' */ rtDW->If1_ActiveSubsystem = -1; - /* Start for IfAction SubSystem: '/F05_Field_Oriented_Control' */ - /* Start for If: '/If2' */ + /* Start for IfAction SubSystem: '/Clarke_Park_Transform_Forward' */ + /* Start for If: '/If2' */ rtDW->If2_ActiveSubsystem_a = -1; - /* Start for If: '/If1' */ - rtDW->If1_ActiveSubsystem_e = -1; + /* End of Start for SubSystem: '/Clarke_Park_Transform_Forward' */ - /* Start for IfAction SubSystem: '/FOC' */ - /* Start for SwitchCase: '/Switch Case' */ + /* Start for Chart: '/Task_Scheduler' incorporates: + * SubSystem: '/F03_Control_Mode_Manager' + */ + /* Start for If: '/If2' */ + rtDW->If2_ActiveSubsystem_f = -1; + + /* Start for Chart: '/Task_Scheduler' incorporates: + * SubSystem: '/Motor_Limitations' + */ + /* Start for If: '/If1' */ + rtDW->If1_ActiveSubsystem_o = -1; + + /* Start for IfAction SubSystem: '/Motor_Limitations_Enabled' */ + /* Start for SwitchCase: '/Switch Case' */ + rtDW->SwitchCase_ActiveSubsystem_d = -1; + + /* End of Start for SubSystem: '/Motor_Limitations_Enabled' */ + + /* Start for Chart: '/Task_Scheduler' incorporates: + * SubSystem: '/FOC' + */ + /* Start for If: '/If1' */ + rtDW->If1_ActiveSubsystem_j = -1; + + /* Start for IfAction SubSystem: '/FOC_Enabled' */ + /* Start for SwitchCase: '/Switch Case' */ rtDW->SwitchCase_ActiveSubsystem = -1; - /* End of Start for SubSystem: '/FOC' */ - /* End of Start for SubSystem: '/F05_Field_Oriented_Control' */ + /* Start for If: '/If1' */ + rtDW->If1_ActiveSubsystem_a = -1; + + /* End of Start for SubSystem: '/FOC_Enabled' */ + + /* Start for If: '/If2' */ + rtDW->If2_ActiveSubsystem = -1; + /* End of Start for SubSystem: '/BLDC_controller' */ /* SystemInitialize for Atomic SubSystem: '/BLDC_controller' */ - /* InitializeConditions for UnitDelay: '/UnitDelay3' */ + /* InitializeConditions for UnitDelay: '/UnitDelay3' */ rtDW->UnitDelay3_DSTATE = rtP->z_maxCntRst; - /* InitializeConditions for UnitDelay: '/UnitDelay2' */ - rtDW->UnitDelay2_DSTATE_g = true; + /* InitializeConditions for UnitDelay: '/UnitDelay2' */ + rtDW->UnitDelay2_DSTATE_c = true; - /* SystemInitialize for IfAction SubSystem: '/Raw_Motor_Speed_Estimation' */ - /* SystemInitialize for Outport: '/z_counter' */ + /* SystemInitialize for IfAction SubSystem: '/Raw_Motor_Speed_Estimation' */ + /* SystemInitialize for Outport: '/z_counter' */ rtDW->z_counterRawPrev = rtP->z_maxCntRst; - /* End of SystemInitialize for SubSystem: '/Raw_Motor_Speed_Estimation' */ + /* End of SystemInitialize for SubSystem: '/Raw_Motor_Speed_Estimation' */ - /* SystemInitialize for Atomic SubSystem: '/Counter' */ + /* SystemInitialize for Atomic SubSystem: '/Counter' */ Counter_Init(&rtDW->Counter_e, rtP->z_maxCntRst); - /* End of SystemInitialize for SubSystem: '/Counter' */ + /* End of SystemInitialize for SubSystem: '/Counter' */ - /* SystemInitialize for IfAction SubSystem: '/F02_Diagnostics' */ + /* SystemInitialize for Chart: '/Task_Scheduler' incorporates: + * SubSystem: '/F02_Diagnostics' + */ - /* SystemInitialize for Atomic SubSystem: '/Debounce_Filter' */ - Debounce_Filter_Init(&rtDW->Debounce_Filter_f); + /* SystemInitialize for IfAction SubSystem: '/Diagnostics_Enabled' */ - /* End of SystemInitialize for SubSystem: '/Debounce_Filter' */ + /* SystemInitialize for Atomic SubSystem: '/Debounce_Filter' */ + Debounce_Filter_Init(&rtDW->Debounce_Filter_k); - /* End of SystemInitialize for SubSystem: '/F02_Diagnostics' */ + /* End of SystemInitialize for SubSystem: '/Debounce_Filter' */ - /* SystemInitialize for IfAction SubSystem: '/F03_Control_Mode_Manager' */ - /* SystemInitialize for IfAction SubSystem: '/Open_Mode' */ - /* SystemInitialize for Atomic SubSystem: '/rising_edge_init' */ - /* InitializeConditions for UnitDelay: '/UnitDelay' */ + /* End of SystemInitialize for SubSystem: '/Diagnostics_Enabled' */ + + /* SystemInitialize for Chart: '/Task_Scheduler' incorporates: + * SubSystem: '/F03_Control_Mode_Manager' + */ + /* SystemInitialize for IfAction SubSystem: '/Open_Mode' */ + /* SystemInitialize for Atomic SubSystem: '/rising_edge_init' */ + /* InitializeConditions for UnitDelay: '/UnitDelay' */ rtDW->UnitDelay_DSTATE_b = true; - /* End of SystemInitialize for SubSystem: '/rising_edge_init' */ - /* End of SystemInitialize for SubSystem: '/Open_Mode' */ - /* End of SystemInitialize for SubSystem: '/F03_Control_Mode_Manager' */ + /* End of SystemInitialize for SubSystem: '/rising_edge_init' */ + /* End of SystemInitialize for SubSystem: '/Open_Mode' */ - /* SystemInitialize for IfAction SubSystem: '/F05_Field_Oriented_Control' */ - /* SystemInitialize for IfAction SubSystem: '/Motor_Limitations' */ + /* SystemInitialize for Chart: '/Task_Scheduler' incorporates: + * SubSystem: '/Motor_Limitations' + */ + /* SystemInitialize for IfAction SubSystem: '/Motor_Limitations_Enabled' */ - /* SystemInitialize for IfAction SubSystem: '/Voltage_Mode_Protection' */ + /* SystemInitialize for IfAction SubSystem: '/Voltage_Mode_Protection' */ - /* SystemInitialize for Atomic SubSystem: '/I_backCalc_fixdt' */ + /* SystemInitialize for Atomic SubSystem: '/I_backCalc_fixdt' */ I_backCalc_fixdt_Init(&rtDW->I_backCalc_fixdt_i, 65536000); - /* End of SystemInitialize for SubSystem: '/I_backCalc_fixdt' */ + /* End of SystemInitialize for SubSystem: '/I_backCalc_fixdt' */ - /* SystemInitialize for Atomic SubSystem: '/I_backCalc_fixdt1' */ + /* SystemInitialize for Atomic SubSystem: '/I_backCalc_fixdt1' */ I_backCalc_fixdt_Init(&rtDW->I_backCalc_fixdt1, 65536000); - /* End of SystemInitialize for SubSystem: '/I_backCalc_fixdt1' */ + /* End of SystemInitialize for SubSystem: '/I_backCalc_fixdt1' */ - /* End of SystemInitialize for SubSystem: '/Voltage_Mode_Protection' */ + /* End of SystemInitialize for SubSystem: '/Voltage_Mode_Protection' */ - /* SystemInitialize for IfAction SubSystem: '/Torque_Mode_Protection' */ + /* SystemInitialize for IfAction SubSystem: '/Torque_Mode_Protection' */ - /* SystemInitialize for Atomic SubSystem: '/I_backCalc_fixdt' */ - I_backCalc_fixdt_Init(&rtDW->I_backCalc_fixdt_g, 58982400); + /* SystemInitialize for Atomic SubSystem: '/I_backCalc_fixdt' */ + I_backCalc_fixdt_Init(&rtDW->I_backCalc_fixdt_j, 58982400); - /* End of SystemInitialize for SubSystem: '/I_backCalc_fixdt' */ + /* End of SystemInitialize for SubSystem: '/I_backCalc_fixdt' */ - /* End of SystemInitialize for SubSystem: '/Torque_Mode_Protection' */ + /* End of SystemInitialize for SubSystem: '/Torque_Mode_Protection' */ - /* SystemInitialize for Outport: '/Vd_max' */ + /* SystemInitialize for Outport: '/Vd_max' */ rtDW->Vd_max1 = 14400; - /* SystemInitialize for Outport: '/Vd_min' */ + /* SystemInitialize for Outport: '/Vd_min' */ rtDW->Gain3 = -14400; - /* SystemInitialize for Outport: '/Vq_max' */ + /* SystemInitialize for Outport: '/Vq_max' */ rtDW->Vq_max_M1 = 14400; - /* SystemInitialize for Outport: '/Vq_min' */ + /* SystemInitialize for Outport: '/Vq_min' */ rtDW->Gain5 = -14400; - /* SystemInitialize for Outport: '/id_max' */ + /* SystemInitialize for Outport: '/id_max' */ rtDW->i_max = 12000; - /* SystemInitialize for Outport: '/id_min' */ - rtDW->Gain4_c = -12000; + /* SystemInitialize for Outport: '/id_min' */ + rtDW->Gain4 = -12000; - /* SystemInitialize for Outport: '/iq_max' */ - rtDW->Divide1_a = 12000; + /* SystemInitialize for Outport: '/iq_max' */ + rtDW->Divide1_n = 12000; - /* SystemInitialize for Outport: '/iq_min' */ + /* SystemInitialize for Outport: '/iq_min' */ rtDW->Gain1 = -12000; - /* End of SystemInitialize for SubSystem: '/Motor_Limitations' */ + /* End of SystemInitialize for SubSystem: '/Motor_Limitations_Enabled' */ - /* SystemInitialize for IfAction SubSystem: '/FOC' */ + /* SystemInitialize for Chart: '/Task_Scheduler' incorporates: + * SubSystem: '/FOC' + */ - /* SystemInitialize for IfAction SubSystem: '/Vd_Calculation' */ + /* SystemInitialize for IfAction SubSystem: '/FOC_Enabled' */ - /* SystemInitialize for Atomic SubSystem: '/PI_clamp_fixdt' */ - PI_clamp_fixdt_Init(&rtDW->PI_clamp_fixdt_k); + /* SystemInitialize for IfAction SubSystem: '/Speed_Mode' */ - /* End of SystemInitialize for SubSystem: '/PI_clamp_fixdt' */ + /* SystemInitialize for Atomic SubSystem: '/PI_clamp_fixdt' */ + PI_clamp_fixdt_d_Init(&rtDW->PI_clamp_fixdt_l4); - /* End of SystemInitialize for SubSystem: '/Vd_Calculation' */ + /* End of SystemInitialize for SubSystem: '/PI_clamp_fixdt' */ - /* SystemInitialize for IfAction SubSystem: '/Speed_Mode' */ + /* End of SystemInitialize for SubSystem: '/Speed_Mode' */ - /* SystemInitialize for Atomic SubSystem: '/PI_clamp_fixdt' */ - PI_clamp_fixdt_g_Init(&rtDW->PI_clamp_fixdt_oc); + /* SystemInitialize for IfAction SubSystem: '/Torque_Mode' */ - /* End of SystemInitialize for SubSystem: '/PI_clamp_fixdt' */ + /* SystemInitialize for Atomic SubSystem: '/PI_clamp_fixdt' */ + PI_clamp_fixdt_f_Init(&rtDW->PI_clamp_fixdt_kh); - /* End of SystemInitialize for SubSystem: '/Speed_Mode' */ + /* End of SystemInitialize for SubSystem: '/PI_clamp_fixdt' */ - /* SystemInitialize for IfAction SubSystem: '/Torque_Mode' */ + /* End of SystemInitialize for SubSystem: '/Torque_Mode' */ - /* SystemInitialize for Atomic SubSystem: '/PI_clamp_fixdt' */ - PI_clamp_fixdt_k_Init(&rtDW->PI_clamp_fixdt_at); + /* SystemInitialize for IfAction SubSystem: '/Vd_Calculation' */ - /* End of SystemInitialize for SubSystem: '/PI_clamp_fixdt' */ + /* SystemInitialize for Atomic SubSystem: '/PI_clamp_fixdt' */ + PI_clamp_fixdt_Init(&rtDW->PI_clamp_fixdt_i); - /* End of SystemInitialize for SubSystem: '/Torque_Mode' */ + /* End of SystemInitialize for SubSystem: '/PI_clamp_fixdt' */ - /* End of SystemInitialize for SubSystem: '/FOC' */ + /* End of SystemInitialize for SubSystem: '/Vd_Calculation' */ + + /* End of SystemInitialize for SubSystem: '/FOC_Enabled' */ - /* End of SystemInitialize for SubSystem: '/F05_Field_Oriented_Control' */ /* End of SystemInitialize for SubSystem: '/BLDC_controller' */ } diff --git a/Src/BLDC_controller_data.c b/Src/BLDC_controller_data.c index f12473d..16686aa 100644 --- a/Src/BLDC_controller_data.c +++ b/Src/BLDC_controller_data.c @@ -3,9 +3,9 @@ * * Code generated for Simulink model 'BLDC_controller'. * - * Model version : 1.1284 + * Model version : 1.1296 * Simulink Coder version : 8.13 (R2017b) 24-Jul-2017 - * C/C++ source code generated on : Sun Oct 11 21:38:56 2020 + * C/C++ source code generated on : Tue Oct 20 17:29:57 2020 * * Target selection: ert.tlc * Embedded hardware selection: ARM Compatible->ARM Cortex @@ -21,8 +21,50 @@ /* Constant parameters (auto storage) */ const ConstP rtConstP = { + /* Computed Parameter: r_sin_M1_Table + * Referenced by: '/r_sin_M1' + */ + { 8192, 8682, 9162, 9630, 10087, 10531, 10963, 11381, 11786, 12176, 12551, + 12911, 13255, 13583, 13894, 14189, 14466, 14726, 14968, 15191, 15396, 15582, + 15749, 15897, 16026, 16135, 16225, 16294, 16344, 16374, 16384, 16374, 16344, + 16294, 16225, 16135, 16026, 15897, 15749, 15582, 15396, 15191, 14968, 14726, + 14466, 14189, 13894, 13583, 13255, 12911, 12551, 12176, 11786, 11381, 10963, + 10531, 10087, 9630, 9162, 8682, 8192, 7692, 7182, 6664, 6138, 5604, 5063, + 4516, 3964, 3406, 2845, 2280, 1713, 1143, 572, 0, -572, -1143, -1713, -2280, + -2845, -3406, -3964, -4516, -5063, -5604, -6138, -6664, -7182, -7692, -8192, + -8682, -9162, -9630, -10087, -10531, -10963, -11381, -11786, -12176, -12551, + -12911, -13255, -13583, -13894, -14189, -14466, -14726, -14968, -15191, + -15396, -15582, -15749, -15897, -16026, -16135, -16225, -16294, -16344, + -16374, -16384, -16374, -16344, -16294, -16225, -16135, -16026, -15897, + -15749, -15582, -15396, -15191, -14968, -14726, -14466, -14189, -13894, + -13583, -13255, -12911, -12551, -12176, -11786, -11381, -10963, -10531, + -10087, -9630, -9162, -8682, -8192, -7692, -7182, -6664, -6138, -5604, -5063, + -4516, -3964, -3406, -2845, -2280, -1713, -1143, -572, 0, 572, 1143, 1713, + 2280, 2845, 3406, 3964, 4516, 5063, 5604, 6138, 6664, 7182, 7692, 8192 }, + + /* Computed Parameter: r_cos_M1_Table + * Referenced by: '/r_cos_M1' + */ + { 14189, 13894, 13583, 13255, 12911, 12551, 12176, 11786, 11381, 10963, 10531, + 10087, 9630, 9162, 8682, 8192, 7692, 7182, 6664, 6138, 5604, 5063, 4516, + 3964, 3406, 2845, 2280, 1713, 1143, 572, 0, -572, -1143, -1713, -2280, -2845, + -3406, -3964, -4516, -5063, -5604, -6138, -6664, -7182, -7692, -8192, -8682, + -9162, -9630, -10087, -10531, -10963, -11381, -11786, -12176, -12551, -12911, + -13255, -13583, -13894, -14189, -14466, -14726, -14968, -15191, -15396, + -15582, -15749, -15897, -16026, -16135, -16225, -16294, -16344, -16374, + -16384, -16374, -16344, -16294, -16225, -16135, -16026, -15897, -15749, + -15582, -15396, -15191, -14968, -14726, -14466, -14189, -13894, -13583, + -13255, -12911, -12551, -12176, -11786, -11381, -10963, -10531, -10087, + -9630, -9162, -8682, -8192, -7692, -7182, -6664, -6138, -5604, -5063, -4516, + -3964, -3406, -2845, -2280, -1713, -1143, -572, 0, 572, 1143, 1713, 2280, + 2845, 3406, 3964, 4516, 5063, 5604, 6138, 6664, 7182, 7692, 8192, 8682, 9162, + 9630, 10087, 10531, 10963, 11381, 11786, 12176, 12551, 12911, 13255, 13583, + 13894, 14189, 14466, 14726, 14968, 15191, 15396, 15582, 15749, 15897, 16026, + 16135, 16225, 16294, 16344, 16374, 16384, 16374, 16344, 16294, 16225, 16135, + 16026, 15897, 15749, 15582, 15396, 15191, 14968, 14726, 14466, 14189 }, + /* Computed Parameter: r_sin3PhaA_M1_Table - * Referenced by: '/r_sin3PhaA_M1' + * Referenced by: '/r_sin3PhaA_M1' */ { -13091, -13634, -14126, -14565, -14953, -15289, -15577, -15816, -16009, -16159, -16269, -16340, -16377, -16383, -16362, -16317, -16253, -16172, @@ -44,7 +86,7 @@ const ConstP rtConstP = { -9623, -10411, -11154, -11849, -12496, -13091 }, /* Computed Parameter: r_sin3PhaB_M1_Table - * Referenced by: '/r_sin3PhaB_M1' + * Referenced by: '/r_sin3PhaB_M1' */ { 15172, 15180, 15206, 15248, 15306, 15377, 15461, 15555, 15656, 15762, 15870, 15977, 16079, 16172, 16253, 16317, 16362, 16383, 16377, 16340, 16269, 16159, @@ -66,7 +108,7 @@ const ConstP rtConstP = { 15377, 15306, 15248, 15206, 15180, 15172 }, /* Computed Parameter: r_sin3PhaC_M1_Table - * Referenced by: '/r_sin3PhaC_M1' + * Referenced by: '/r_sin3PhaC_M1' */ { -13091, -12496, -11849, -11154, -10411, -9623, -8791, -7921, -7014, -6075, -5107, -4115, -3104, -2077, -1041, 0, 1041, 2077, 3104, 4115, 5107, 6075, @@ -87,50 +129,8 @@ const ConstP rtConstP = { -16362, -16383, -16377, -16340, -16269, -16159, -16009, -15816, -15577, -15289, -14953, -14565, -14126, -13634, -13091 }, - /* Computed Parameter: r_sin_M1_Table - * Referenced by: '/r_sin_M1' - */ - { 8192, 8682, 9162, 9630, 10087, 10531, 10963, 11381, 11786, 12176, 12551, - 12911, 13255, 13583, 13894, 14189, 14466, 14726, 14968, 15191, 15396, 15582, - 15749, 15897, 16026, 16135, 16225, 16294, 16344, 16374, 16384, 16374, 16344, - 16294, 16225, 16135, 16026, 15897, 15749, 15582, 15396, 15191, 14968, 14726, - 14466, 14189, 13894, 13583, 13255, 12911, 12551, 12176, 11786, 11381, 10963, - 10531, 10087, 9630, 9162, 8682, 8192, 7692, 7182, 6664, 6138, 5604, 5063, - 4516, 3964, 3406, 2845, 2280, 1713, 1143, 572, 0, -572, -1143, -1713, -2280, - -2845, -3406, -3964, -4516, -5063, -5604, -6138, -6664, -7182, -7692, -8192, - -8682, -9162, -9630, -10087, -10531, -10963, -11381, -11786, -12176, -12551, - -12911, -13255, -13583, -13894, -14189, -14466, -14726, -14968, -15191, - -15396, -15582, -15749, -15897, -16026, -16135, -16225, -16294, -16344, - -16374, -16384, -16374, -16344, -16294, -16225, -16135, -16026, -15897, - -15749, -15582, -15396, -15191, -14968, -14726, -14466, -14189, -13894, - -13583, -13255, -12911, -12551, -12176, -11786, -11381, -10963, -10531, - -10087, -9630, -9162, -8682, -8192, -7692, -7182, -6664, -6138, -5604, -5063, - -4516, -3964, -3406, -2845, -2280, -1713, -1143, -572, 0, 572, 1143, 1713, - 2280, 2845, 3406, 3964, 4516, 5063, 5604, 6138, 6664, 7182, 7692, 8192 }, - - /* Computed Parameter: r_cos_M1_Table - * Referenced by: '/r_cos_M1' - */ - { 14189, 13894, 13583, 13255, 12911, 12551, 12176, 11786, 11381, 10963, 10531, - 10087, 9630, 9162, 8682, 8192, 7692, 7182, 6664, 6138, 5604, 5063, 4516, - 3964, 3406, 2845, 2280, 1713, 1143, 572, 0, -572, -1143, -1713, -2280, -2845, - -3406, -3964, -4516, -5063, -5604, -6138, -6664, -7182, -7692, -8192, -8682, - -9162, -9630, -10087, -10531, -10963, -11381, -11786, -12176, -12551, -12911, - -13255, -13583, -13894, -14189, -14466, -14726, -14968, -15191, -15396, - -15582, -15749, -15897, -16026, -16135, -16225, -16294, -16344, -16374, - -16384, -16374, -16344, -16294, -16225, -16135, -16026, -15897, -15749, - -15582, -15396, -15191, -14968, -14726, -14466, -14189, -13894, -13583, - -13255, -12911, -12551, -12176, -11786, -11381, -10963, -10531, -10087, - -9630, -9162, -8682, -8192, -7692, -7182, -6664, -6138, -5604, -5063, -4516, - -3964, -3406, -2845, -2280, -1713, -1143, -572, 0, 572, 1143, 1713, 2280, - 2845, 3406, 3964, 4516, 5063, 5604, 6138, 6664, 7182, 7692, 8192, 8682, 9162, - 9630, 10087, 10531, 10963, 11381, 11786, 12176, 12551, 12911, 13255, 13583, - 13894, 14189, 14466, 14726, 14968, 15191, 15396, 15582, 15749, 15897, 16026, - 16135, 16225, 16294, 16344, 16374, 16384, 16374, 16344, 16294, 16225, 16135, - 16026, 15897, 15749, 15582, 15396, 15191, 14968, 14726, 14466, 14189 }, - /* Computed Parameter: iq_maxSca_M1_Table - * Referenced by: '/iq_maxSca_M1' + * Referenced by: '/iq_maxSca_M1' */ { 65535U, 65523U, 65484U, 65418U, 65326U, 65207U, 65062U, 64890U, 64691U, 64465U, 64211U, 63930U, 63620U, 63281U, 62913U, 62516U, 62088U, 61630U, @@ -140,71 +140,71 @@ const ConstP rtConstP = { 28540U, 25655U, 22323U, 18304U, 12974U }, /* Computed Parameter: z_commutMap_M1_table - * Referenced by: '/z_commutMap_M1' + * Referenced by: '/z_commutMap_M1' */ { -1, 1, 0, -1, 0, 1, 0, -1, 1, 1, -1, 0, 1, 0, -1, 0, 1, -1 }, /* Computed Parameter: vec_hallToPos_Value - * Referenced by: '/vec_hallToPos' + * Referenced by: '/vec_hallToPos' */ { 0, 2, 0, 1, 4, 3, 5, 0 } }; P rtP_Left = { /* Variable: dV_openRate - * Referenced by: '/dV_openRate' + * Referenced by: '/dV_openRate' */ 12288, /* Variable: dz_cntTrnsDetHi - * Referenced by: '/dz_cntTrnsDet' + * Referenced by: '/dz_cntTrnsDet' */ 40, /* Variable: dz_cntTrnsDetLo - * Referenced by: '/dz_cntTrnsDet' + * Referenced by: '/dz_cntTrnsDet' */ 20, /* Variable: n_cruiseMotTgt - * Referenced by: '/n_cruiseMotTgt' + * Referenced by: '/n_cruiseMotTgt' */ 0, /* Variable: z_maxCntRst * Referenced by: - * '/Counter' - * '/z_maxCntRst' - * '/z_maxCntRst2' - * '/UnitDelay3' - * '/z_counter' + * '/Counter' + * '/z_maxCntRst' + * '/z_maxCntRst2' + * '/UnitDelay3' + * '/z_counter' */ 2000, /* Variable: cf_speedCoef - * Referenced by: '/cf_speedCoef' + * Referenced by: '/cf_speedCoef' */ 10667U, /* Variable: t_errDequal - * Referenced by: '/t_errDequal' + * Referenced by: '/t_errDequal' */ 9600U, /* Variable: t_errQual - * Referenced by: '/t_errQual' + * Referenced by: '/t_errQual' */ 1280U, /* Variable: Vd_max * Referenced by: - * '/Vd_max1' - * '/Vd_max' + * '/Vd_max' + * '/Vd_max1' */ 14400, /* Variable: Vq_max_M1 - * Referenced by: '/Vq_max_M1' + * Referenced by: '/Vq_max_M1' */ { 14400, 14396, 14386, 14368, 14343, 14311, 14271, 14225, 14171, 14109, 14040, 13963, 13879, 13786, 13685, 13576, 13459, 13333, 13198, 13053, 12900, 12736, @@ -212,7 +212,7 @@ P rtP_Left = { 9790, 9433, 9051, 8640, 8196, 7713, 7184, 6597, 5935, 5170, 4245, 3019, 0 }, /* Variable: Vq_max_XA - * Referenced by: '/Vq_max_XA' + * Referenced by: '/Vq_max_XA' */ { 0, 320, 640, 960, 1280, 1600, 1920, 2240, 2560, 2880, 3200, 3520, 3840, 4160, 4480, 4800, 5120, 5440, 5760, 6080, 6400, 6720, 7040, 7360, 7680, 8000, 8320, @@ -220,127 +220,127 @@ P rtP_Left = { 12160, 12480, 12800, 13120, 13440, 13760, 14080, 14400 }, /* Variable: a_phaAdvMax - * Referenced by: '/a_phaAdvMax' + * Referenced by: '/a_phaAdvMax' */ 400, /* Variable: i_max * Referenced by: - * '/i_max' - * '/i_max' + * '/i_max' + * '/i_max' */ 12000, /* Variable: id_fieldWeakMax - * Referenced by: '/id_fieldWeakMax' + * Referenced by: '/id_fieldWeakMax' */ 4000, /* Variable: n_commAcvLo - * Referenced by: '/n_commDeacv' + * Referenced by: '/n_commDeacv' */ 240, /* Variable: n_commDeacvHi - * Referenced by: '/n_commDeacv' + * Referenced by: '/n_commDeacv' */ 480, /* Variable: n_fieldWeakAuthHi - * Referenced by: '/n_fieldWeakAuthHi' + * Referenced by: '/n_fieldWeakAuthHi' */ 6400, /* Variable: n_fieldWeakAuthLo - * Referenced by: '/n_fieldWeakAuthLo' + * Referenced by: '/n_fieldWeakAuthLo' */ 4800, /* Variable: n_max * Referenced by: - * '/n_max1' - * '/n_max' + * '/n_max' + * '/n_max1' */ - 24000, + 16000, /* Variable: n_stdStillDet - * Referenced by: '/n_stdStillDet' + * Referenced by: '/n_stdStillDet' */ 48, /* Variable: r_errInpTgtThres - * Referenced by: '/r_errInpTgtThres' + * Referenced by: '/r_errInpTgtThres' */ 9600, /* Variable: r_fieldWeakHi - * Referenced by: '/r_fieldWeakHi' + * Referenced by: '/r_fieldWeakHi' */ 16000, /* Variable: r_fieldWeakLo - * Referenced by: '/r_fieldWeakLo' + * Referenced by: '/r_fieldWeakLo' */ 12000, /* Variable: cf_KbLimProt * Referenced by: - * '/cf_KbLimProt' - * '/cf_KbLimProt' + * '/cf_KbLimProt' + * '/cf_KbLimProt' */ 768U, /* Variable: cf_idKp - * Referenced by: '/cf_idKp1' + * Referenced by: '/cf_idKp1' */ 819U, /* Variable: cf_iqKp - * Referenced by: '/cf_iqKp' + * Referenced by: '/cf_iqKp' */ 1229U, /* Variable: cf_nKp - * Referenced by: '/cf_nKp' + * Referenced by: '/cf_nKp' */ 4833U, /* Variable: cf_currFilt - * Referenced by: '/cf_currFilt' + * Referenced by: '/cf_currFilt' */ 7864U, /* Variable: cf_idKi - * Referenced by: '/cf_idKi1' + * Referenced by: '/cf_idKi1' */ 737U, /* Variable: cf_iqKi - * Referenced by: '/cf_iqKi' + * Referenced by: '/cf_iqKi' */ 1229U, /* Variable: cf_iqKiLimProt * Referenced by: - * '/cf_iqKiLimProt' - * '/cf_iqKiLimProt' + * '/cf_iqKiLimProt' + * '/cf_iqKiLimProt' */ 737U, /* Variable: cf_nKi - * Referenced by: '/cf_nKi' + * Referenced by: '/cf_nKi' */ 251U, /* Variable: cf_nKiLimProt * Referenced by: - * '/cf_nKiLimProt' - * '/cf_nKiLimProt' + * '/cf_nKiLimProt' + * '/cf_nKiLimProt' */ 246U, /* Variable: n_polePairs - * Referenced by: '/n_polePairs' + * Referenced by: '/n_polePairs' */ 15U, @@ -350,14 +350,14 @@ P rtP_Left = { 2U, /* Variable: z_selPhaCurMeasABC - * Referenced by: '/z_selPhaCurMeasABC' + * Referenced by: '/z_selPhaCurMeasABC' */ 0U, /* Variable: b_angleMeasEna * Referenced by: - * '/b_angleMeasEna' - * '/b_angleMeasEna' + * '/b_angleMeasEna' + * '/b_angleMeasEna' */ 0, @@ -367,14 +367,14 @@ P rtP_Left = { 0, /* Variable: b_diagEna - * Referenced by: '/b_diagEna' + * Referenced by: '/b_diagEna' */ 1, /* Variable: b_fieldWeakEna * Referenced by: - * '/b_fieldWeakEna' - * '/b_fieldWeakEna' + * '/b_fieldWeakEna' + * '/b_fieldWeakEna' */ 0 }; /* Modifiable parameters */