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change comment for rlow

This commit is contained in:
interfisch 2019-07-10 10:45:29 +02:00
parent e6ebff4b5d
commit f6fdeafd37
2 changed files with 21 additions and 21 deletions
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40
schematic/mixerin_output/mixerin_output.kicad_pcb
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@ -11,8 +11,8 @@
(page A4)
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(31 B.Cu signal)
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(31 B.Cu signal hide)
(32 B.Adhes user)
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(34 B.Paste user)
@ -152,7 +152,7 @@
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@ -205,7 +205,7 @@
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@ -342,7 +342,7 @@
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@ -383,7 +383,7 @@
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@ -424,7 +424,7 @@
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@ -465,7 +465,7 @@
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@ -506,7 +506,7 @@
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@ -547,7 +547,7 @@
(fp_text reference RB2 (at 1.905 -1.905 90) (layer F.SilkS)
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@ -588,7 +588,7 @@
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@ -629,7 +629,7 @@
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@ -670,7 +670,7 @@
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@ -711,7 +711,7 @@
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@ -749,7 +749,7 @@
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.0mm width 1.6mm Capacitor")
(path /5C54CB2B)
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@ -787,7 +787,7 @@
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@ -859,7 +859,7 @@
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@ -896,7 +896,7 @@
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@ -937,7 +937,7 @@
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@ -1073,7 +1073,7 @@
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2
schematic/mixerin_output/mixerin_output.sch
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@ -611,7 +611,7 @@ Connection ~ 4450 5500
Connection ~ 1300 1700
Connection ~ 1300 1100
Text Notes 3950 4350 0 50 ~ 0
For output stage configuration:\nRA5,RB5=Rlow for minimum offset error\ndue to input bias current.\nRlow = R1//R2//R3 ... (inputs)
For output stage configuration:\nRA3,RB3=Rlow for minimum offset error\ndue to input bias current.\nRlow = R1//R2//R3 ... (inputs)
Wire Wire Line
3650 3750 3850 3750
$Comp