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widen silkscreen on pcie connector footprint

This commit is contained in:
interfisch 2019-06-18 11:54:05 +02:00
parent 6d4bcda40f
commit 0d44c045f2
6 changed files with 357 additions and 185 deletions
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8
schematic/baseplate_in_output/baseplate_in_output.bak
View File

@ -593,7 +593,7 @@ U 1 1 5CD1356B
P 3550 1900
F 0 "J9" H 3150 1900 50 0000 C CNN
F 1 "GND" H 3400 1900 50 0000 C CNN
F 2 "footprints:edge_solderstrip_1mm5x6mm" H 3550 1900 50 0001 C CNN
F 2 "footprints:edge_solderstrip_th" H 3550 1900 50 0001 C CNN
F 3 "~" H 3550 1900 50 0001 C CNN
1 3550 1900
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@ -604,7 +604,7 @@ U 1 1 5CD1363E
P 3550 2000
F 0 "J10" H 3150 2000 50 0000 C CNN
F 1 "GND" H 3400 2000 50 0000 C CNN
F 2 "footprints:edge_solderstrip_1mm5x6mm" H 3550 2000 50 0001 C CNN
F 2 "footprints:edge_solderstrip_th" H 3550 2000 50 0001 C CNN
F 3 "~" H 3550 2000 50 0001 C CNN
1 3550 2000
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@ -615,7 +615,7 @@ U 1 1 5CD13668
P 3550 2100
F 0 "J11" H 3150 2100 50 0000 C CNN
F 1 "GND" H 3400 2100 50 0000 C CNN
F 2 "footprints:edge_solderstrip_1mm5x6mm" H 3550 2100 50 0001 C CNN
F 2 "footprints:edge_solderstrip_th" H 3550 2100 50 0001 C CNN
F 3 "~" H 3550 2100 50 0001 C CNN
1 3550 2100
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@ -626,7 +626,7 @@ U 1 1 5CD13694
P 3550 1800
F 0 "J8" H 3150 1800 50 0000 C CNN
F 1 "GND" H 3400 1800 50 0000 C CNN
F 2 "footprints:edge_solderstrip_1mm5x6mm" H 3550 1800 50 0001 C CNN
F 2 "footprints:edge_solderstrip_th" H 3550 1800 50 0001 C CNN
F 3 "~" H 3550 1800 50 0001 C CNN
1 3550 1800
1 0 0 -1

180
schematic/baseplate_in_output/baseplate_in_output.kicad_pcb
View File

@ -62,12 +62,12 @@
(aux_axis_origin 0 0)
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(pcbplotparams
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(layerselection 0x010f0_ffffffff)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(excludeedgelayer false)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
@ -81,13 +81,13 @@
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(padsonsilk true)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
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(scaleselection 1)
(outputdirectory ""))
(outputdirectory "plots/"))
)
(net 0 "")
@ -119,7 +119,7 @@
(add_net outB)
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(module footprints:PCIexpress_1x_connector (layer F.Cu) (tedit 5CD00FC7) (tstamp 5CB1E174)
(module footprints:PCIexpress_1x_connector (layer F.Cu) (tedit 5D08AB2A) (tstamp 5CB1E174)
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(path /5CB5100B)
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@ -128,87 +128,87 @@
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(pad 11a thru_hole circle (at 10 0 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 1 GNDA))
(pad 12a thru_hole circle (at 13 -2 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
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(pad "" thru_hole circle (at 20.65 1.25 90) (size 2.35 2.35) (drill 2.35) (layers *.Cu *.Mask))
)
(module footprints:coax_solder_pad (layer F.Cu) (tedit 5CB36FFB) (tstamp 5CB1E198)
@ -553,7 +553,6 @@
(segment (start 41.6 41.72) (end 42.6 40.72) (width 1) (layer F.Cu) (net 1))
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@ -591,6 +590,7 @@
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@ -628,13 +628,13 @@
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@ -649,15 +649,15 @@
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(zone (net 1) (net_name GNDA) (layer B.Cu) (tstamp 0) (hatch edge 0.508)
(zone (net 1) (net_name GNDA) (layer B.Cu) (tstamp 5D08B0C1) (hatch edge 0.508)
(connect_pads (clearance 0.5))
(min_thickness 1.45)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 1.5))
@ -680,8 +680,8 @@
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338
schematic/baseplate_in_output/baseplate_in_output.kicad_pcb-bak
View File

@ -119,7 +119,7 @@
(add_net outB)
)
(module footprints:PCIexpress_1x_connector (layer F.Cu) (tedit 5CD00FC7) (tstamp 5CB1E174)
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4
schematic/baseplate_in_output/baseplate_in_output.net
View File

@ -1,7 +1,7 @@
(export (version D)
(design
(source /media/fisch/HDD/Projects/mixer/schematic/baseplate_in_output/baseplate_in_output.sch)
(date "Mo 06 Mai 2019 13:28:12 CEST")
(source /media/fisch/HDD/Projects/audiomixer/schematic/baseplate_in_output/baseplate_in_output.sch)
(date "Di 18 Jun 2019 11:16:57 CEST")
(tool "Eeschema 5.0.2-bee76a0~70~ubuntu16.04.1")
(sheet (number 1) (name /) (tstamps /)
(title_block

2
schematic/baseplate_in_output/fp-lib-table
View File

@ -1,3 +1,3 @@
(fp_lib_table
(lib (name footprints)(type KiCad)(uri /media/fisch/HDD/Projects/mixer/schematic/footprints)(options "")(descr ""))
(lib (name footprints)(type KiCad)(uri /media/fisch/HDD/Projects/audiomixer/schematic/footprints)(options "")(descr ""))
)

10
schematic/footprints/PCIexpress_1x_connector.kicad_mod
View File

@ -1,4 +1,4 @@
(module PCIexpress_1x_connector (layer F.Cu) (tedit 5CB1C54C)
(module PCIexpress_1x_connector (layer F.Cu) (tedit 5D08AB2A)
(fp_text reference REF** (at -14.28 5.355) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
@ -8,10 +8,10 @@
(fp_line (start -3 5.5) (end -3 5) (layer F.SilkS) (width 0.15))
(fp_line (start 22 5.5) (end -3 5.5) (layer F.SilkS) (width 0.15))
(fp_line (start 22 5) (end 22 5.5) (layer F.SilkS) (width 0.15))
(fp_line (start -3 5) (end -3 -2.5) (layer F.SilkS) (width 0.15))
(fp_line (start 22 5) (end -3 5) (layer F.SilkS) (width 0.15))
(fp_line (start 22 -2.5) (end 22 5) (layer F.SilkS) (width 0.15))
(fp_line (start -3 -2.5) (end 22 -2.5) (layer F.SilkS) (width 0.15))
(fp_line (start -3 5) (end -3 -2.8) (layer F.SilkS) (width 0.15))
(fp_line (start 22 5.3) (end -3 5.3) (layer F.SilkS) (width 0.15))
(fp_line (start 22 -2.8) (end 22 5) (layer F.SilkS) (width 0.15))
(fp_line (start -3 -2.8) (end 22 -2.8) (layer F.SilkS) (width 0.15))
(pad "" thru_hole circle (at 20.65 1.25) (size 2.35 2.35) (drill 2.35) (layers *.Cu *.Mask))
(pad "" thru_hole circle (at 11.65 1.25) (size 2.35 2.35) (drill 2.35) (layers *.Cu *.Mask))
(pad 18b thru_hole circle (at 19 4.5) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask))