2699 lines
116 KiB
C
Executable File
2699 lines
116 KiB
C
Executable File
/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F4xx/stm32_registry.h
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* @brief STM32F4xx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef STM32_REGISTRY_H
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#define STM32_REGISTRY_H
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#if defined(STM32F469xx) || defined(STM32F479xx)
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#define STM32F469_479xx
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#define STM32F4XX
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#elif defined(STM32F446xx)
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#define STM32F4XX
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#elif defined(STM32F439xx) || defined(STM32F429xx)
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#define STM32F429_439xx
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#define STM32F4XX
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#elif defined(STM32F437xx) || defined(STM32F427xx)
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#define STM32F427_437xx
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#define STM32F4XX
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#elif defined(STM32F412Cx) || defined(STM32F412Rx) || \
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defined(STM32F412Vx) || defined(STM32F412Zx)
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#define STM32F412xx
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#define STM32F4XX
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#elif defined(STM32F411xE)
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#define STM32F411xx
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#define STM32F4XX
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#elif defined(STM32F410Cx) || defined(STM32F410Rx) || \
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defined(STM32F410Tx)
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#define STM32F410xx
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#define STM32F4XX
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#elif defined(STM32F405xx) || defined(STM32F415xx) || \
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defined(STM32F407xx) || defined(STM32F417xx)
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#define STM32F40_41xxx
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#define STM32F4XX
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#elif defined(STM32F401xC) || defined(STM32F401xE)
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#define STM32F401xx
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#define STM32F4XX
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#elif defined(STM32F205xx) || defined(STM32F215xx) || \
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defined(STM32F207xx) || defined(STM32F217xx)
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#define STM32F2XX
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#else
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#error "STM32F2xx/F4xx device not specified"
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#endif
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32F4xx/STM32F2xx capabilities
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* @{
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*/
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/*===========================================================================*/
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/* STM32F469xx, STM32F479xx. */
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/*===========================================================================*/
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#if defined(STM32F469_479xx) || defined(__DOXYGEN__)
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/* ADC attributes.*/
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#define STM32_ADC_HANDLER Vector88
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#define STM32_ADC_NUMBER 18
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 TRUE
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#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_ADC2_DMA_CHN 0x00001100
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#define STM32_HAS_ADC3 TRUE
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#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 1))
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#define STM32_ADC3_DMA_CHN 0x00000022
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#define STM32_HAS_ADC4 FALSE
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#define STM32_HAS_SDADC1 FALSE
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#define STM32_HAS_SDADC2 FALSE
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#define STM32_HAS_SDADC3 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN2 TRUE
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#define STM32_HAS_CAN3 FALSE
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#define STM32_CAN_MAX_FILTERS 28
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_DAC1_CH1_DMA_CHN 0x00700000
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_DAC1_CH2_DMA_CHN 0x07000000
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_CACHE_HANDLING FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_DMA1_CH0_HANDLER Vector6C
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#define STM32_DMA1_CH1_HANDLER Vector70
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#define STM32_DMA1_CH2_HANDLER Vector74
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#define STM32_DMA1_CH3_HANDLER Vector78
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#define STM32_DMA1_CH4_HANDLER Vector7C
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#define STM32_DMA1_CH5_HANDLER Vector80
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#define STM32_DMA1_CH6_HANDLER Vector84
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#define STM32_DMA1_CH7_HANDLER VectorFC
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#define STM32_DMA1_CH0_NUMBER 11
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#define STM32_DMA1_CH1_NUMBER 12
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#define STM32_DMA1_CH2_NUMBER 13
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#define STM32_DMA1_CH3_NUMBER 14
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#define STM32_DMA1_CH4_NUMBER 15
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#define STM32_DMA1_CH5_NUMBER 16
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#define STM32_DMA1_CH6_NUMBER 17
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#define STM32_DMA1_CH7_NUMBER 47
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#define STM32_HAS_DMA2 TRUE
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#define STM32_DMA2_CH0_HANDLER Vector120
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#define STM32_DMA2_CH1_HANDLER Vector124
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#define STM32_DMA2_CH2_HANDLER Vector128
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#define STM32_DMA2_CH3_HANDLER Vector12C
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#define STM32_DMA2_CH4_HANDLER Vector130
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#define STM32_DMA2_CH5_HANDLER Vector150
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#define STM32_DMA2_CH6_HANDLER Vector154
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#define STM32_DMA2_CH7_HANDLER Vector158
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#define STM32_DMA2_CH0_NUMBER 56
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#define STM32_DMA2_CH1_NUMBER 57
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#define STM32_DMA2_CH2_NUMBER 58
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#define STM32_DMA2_CH3_NUMBER 59
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#define STM32_DMA2_CH4_NUMBER 60
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#define STM32_DMA2_CH5_NUMBER 68
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#define STM32_DMA2_CH6_NUMBER 69
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#define STM32_DMA2_CH7_NUMBER 70
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_LINES 23
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#define STM32_EXTI_IMR_MASK 0x00000000U
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOH TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOI TRUE
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#define STM32_HAS_GPIOJ TRUE
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#define STM32_HAS_GPIOK TRUE
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#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
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RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | \
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RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN | \
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RCC_AHB1ENR_GPIOFEN | \
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RCC_AHB1ENR_GPIOGEN | \
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RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOIEN | \
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RCC_AHB1ENR_GPIOJEN | \
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RCC_AHB1ENR_GPIOKEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
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STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C1_RX_DMA_CHN 0x00100001
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
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STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_I2C1_TX_DMA_CHN 0x11000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_I2C2_RX_DMA_CHN 0x00007700
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#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
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#define STM32_I2C2_TX_DMA_CHN 0x70000000
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#define STM32_HAS_I2C3 TRUE
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#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_I2C3_RX_DMA_CHN 0x00000300
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#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_I2C3_TX_DMA_CHN 0x00030000
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#define STM32_HAS_I2C4 FALSE
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/* QUADSPI attributes.*/
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#define STM32_HAS_QUADSPI1 TRUE
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#define STM32_QUADSPI1_HANDLER Vector1AC
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#define STM32_QUADSPI1_NUMBER 91
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#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
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#define STM32_QUADSPI1_DMA_CHN 0x30000000
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO TRUE
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#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_SDC_SDIO_DMA_CHN 0x04004000
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S FALSE
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#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 2))
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#define STM32_SPI1_RX_DMA_CHN 0x00000303
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#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_SPI1_TX_DMA_CHN 0x00303000
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_SUPPORTS_I2S TRUE
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#define STM32_SPI2_I2S_FULLDUPLEX TRUE
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#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_SPI2_RX_DMA_CHN 0x00000000
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#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_SPI2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_SUPPORTS_I2S TRUE
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#define STM32_SPI3_I2S_FULLDUPLEX TRUE
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#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
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STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_SPI3_RX_DMA_CHN 0x00000000
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#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
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STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_SPI3_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI4 TRUE
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#define STM32_SPI4_SUPPORTS_I2S FALSE
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#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_SPI4_RX_DMA_CHN 0x00005004
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#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_SPI4_TX_DMA_CHN 0x00050040
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#define STM32_HAS_SPI5 TRUE
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#define STM32_SPI5_SUPPORTS_I2S FALSE
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#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_SPI5_RX_DMA_CHN 0x00702000
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#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_SPI5_TX_DMA_CHN 0x07020000
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#define STM32_HAS_SPI6 TRUE
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#define STM32_SPI6_SUPPORTS_I2S FALSE
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#define STM32_SPI6_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6)
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#define STM32_SPI6_RX_DMA_CHN 0x01000000
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#define STM32_SPI6_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5)
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#define STM32_SPI6_TX_DMA_CHN 0x00100000
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 4
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_HAS_TIM5 TRUE
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#define STM32_TIM5_IS_32BITS TRUE
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#define STM32_TIM5_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM8 TRUE
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#define STM32_TIM8_IS_32BITS FALSE
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#define STM32_TIM8_CHANNELS 4
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#define STM32_HAS_TIM9 TRUE
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#define STM32_TIM9_IS_32BITS FALSE
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#define STM32_TIM9_CHANNELS 2
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#define STM32_HAS_TIM10 TRUE
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#define STM32_TIM10_IS_32BITS FALSE
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#define STM32_TIM10_CHANNELS 1
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#define STM32_HAS_TIM11 TRUE
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#define STM32_TIM11_IS_32BITS FALSE
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#define STM32_TIM11_CHANNELS 1
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#define STM32_HAS_TIM12 TRUE
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#define STM32_TIM12_IS_32BITS FALSE
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#define STM32_TIM12_CHANNELS 2
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#define STM32_HAS_TIM13 TRUE
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#define STM32_TIM13_IS_32BITS FALSE
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#define STM32_TIM13_CHANNELS 1
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 1
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM16 FALSE
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#define STM32_HAS_TIM17 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_USART1_RX_DMA_CHN 0x00400400
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#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
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#define STM32_USART1_TX_DMA_CHN 0x40000000
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#define STM32_HAS_USART2 TRUE
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#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_USART2_RX_DMA_CHN 0x00400000
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#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
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#define STM32_USART2_TX_DMA_CHN 0x04000000
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#define STM32_HAS_USART3 TRUE
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#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
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#define STM32_USART3_RX_DMA_CHN 0x00000040
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#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
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STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_USART3_TX_DMA_CHN 0x00074000
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#define STM32_HAS_UART4 TRUE
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#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_UART4_RX_DMA_CHN 0x00000400
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#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_UART4_TX_DMA_CHN 0x00040000
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#define STM32_HAS_UART5 TRUE
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#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
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#define STM32_UART5_RX_DMA_CHN 0x00000004
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#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
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#define STM32_UART5_TX_DMA_CHN 0x40000000
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#define STM32_HAS_USART6 TRUE
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#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 2))
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#define STM32_USART6_RX_DMA_CHN 0x00000550
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#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_USART6_TX_DMA_CHN 0x55000000
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#define STM32_HAS_UART7 TRUE
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#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_UART7_RX_DMA_CHN 0x00004000
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#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
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#define STM32_UART7_TX_DMA_CHN 0x00000050
|
|
|
|
#define STM32_HAS_UART8 TRUE
|
|
#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
|
#define STM32_UART8_RX_DMA_CHN 0x05000000
|
|
#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
|
|
#define STM32_UART8_TX_DMA_CHN 0x00000005
|
|
#define STM32_HAS_LPUART1 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_OTG_STEPPING 2
|
|
#define STM32_HAS_OTG1 TRUE
|
|
#define STM32_OTG1_ENDPOINTS 5
|
|
#define STM32_HAS_OTG2 TRUE
|
|
#define STM32_OTG2_ENDPOINTS 7
|
|
|
|
#define STM32_HAS_USB FALSE
|
|
|
|
/* IWDG attributes.*/
|
|
#define STM32_HAS_IWDG TRUE
|
|
#define STM32_IWDG_IS_WINDOWED FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC TRUE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D TRUE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC TRUE
|
|
#define STM32_FSMC_IS_FMC TRUE
|
|
#define STM32_FSMC_HANDLER Vector100
|
|
#define STM32_FSMC_NUMBER 48
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE FALSE
|
|
|
|
#endif /* defined(STM32F469_479xx) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F446xx. */
|
|
/*===========================================================================*/
|
|
|
|
#if defined(STM32F446xx)
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_ADC_HANDLER Vector88
|
|
#define STM32_ADC_NUMBER 18
|
|
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_ADC1_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_ADC2 TRUE
|
|
#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3))
|
|
#define STM32_ADC2_DMA_CHN 0x00001100
|
|
|
|
#define STM32_HAS_ADC3 TRUE
|
|
#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 1))
|
|
#define STM32_ADC3_DMA_CHN 0x00000022
|
|
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 TRUE
|
|
#define STM32_HAS_CAN3 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 28
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
|
#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_DAC1_CH1_DMA_CHN 0x00700000
|
|
|
|
#define STM32_HAS_DAC1_CH2 TRUE
|
|
#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_DAC1_CH2_DMA_CHN 0x07000000
|
|
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_CACHE_HANDLING FALSE
|
|
|
|
#define STM32_HAS_DMA1 TRUE
|
|
#define STM32_DMA1_CH0_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_HANDLER Vector70
|
|
#define STM32_DMA1_CH2_HANDLER Vector74
|
|
#define STM32_DMA1_CH3_HANDLER Vector78
|
|
#define STM32_DMA1_CH4_HANDLER Vector7C
|
|
#define STM32_DMA1_CH5_HANDLER Vector80
|
|
#define STM32_DMA1_CH6_HANDLER Vector84
|
|
#define STM32_DMA1_CH7_HANDLER VectorFC
|
|
#define STM32_DMA1_CH0_NUMBER 11
|
|
#define STM32_DMA1_CH1_NUMBER 12
|
|
#define STM32_DMA1_CH2_NUMBER 13
|
|
#define STM32_DMA1_CH3_NUMBER 14
|
|
#define STM32_DMA1_CH4_NUMBER 15
|
|
#define STM32_DMA1_CH5_NUMBER 16
|
|
#define STM32_DMA1_CH6_NUMBER 17
|
|
#define STM32_DMA1_CH7_NUMBER 47
|
|
|
|
#define STM32_HAS_DMA2 TRUE
|
|
#define STM32_DMA2_CH0_HANDLER Vector120
|
|
#define STM32_DMA2_CH1_HANDLER Vector124
|
|
#define STM32_DMA2_CH2_HANDLER Vector128
|
|
#define STM32_DMA2_CH3_HANDLER Vector12C
|
|
#define STM32_DMA2_CH4_HANDLER Vector130
|
|
#define STM32_DMA2_CH5_HANDLER Vector150
|
|
#define STM32_DMA2_CH6_HANDLER Vector154
|
|
#define STM32_DMA2_CH7_HANDLER Vector158
|
|
#define STM32_DMA2_CH0_NUMBER 56
|
|
#define STM32_DMA2_CH1_NUMBER 57
|
|
#define STM32_DMA2_CH2_NUMBER 58
|
|
#define STM32_DMA2_CH3_NUMBER 59
|
|
#define STM32_DMA2_CH4_NUMBER 60
|
|
#define STM32_DMA2_CH5_NUMBER 68
|
|
#define STM32_DMA2_CH6_NUMBER 69
|
|
#define STM32_DMA2_CH7_NUMBER 70
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 23
|
|
#define STM32_EXTI_IMR_MASK 0x00000000U
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE TRUE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG TRUE
|
|
#define STM32_HAS_GPIOH TRUE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
|
|
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
|
|
RCC_AHB1ENR_GPIOBEN | \
|
|
RCC_AHB1ENR_GPIOCEN | \
|
|
RCC_AHB1ENR_GPIODEN | \
|
|
RCC_AHB1ENR_GPIOEEN | \
|
|
RCC_AHB1ENR_GPIOFEN | \
|
|
RCC_AHB1ENR_GPIOGEN | \
|
|
RCC_AHB1ENR_GPIOHEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_I2C1_RX_DMA_CHN 0x00100001
|
|
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_I2C1_TX_DMA_CHN 0x11000000
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3))
|
|
#define STM32_I2C2_RX_DMA_CHN 0x00007700
|
|
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_I2C2_TX_DMA_CHN 0x70000000
|
|
|
|
#define STM32_HAS_I2C3 TRUE
|
|
#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_I2C3_RX_DMA_CHN 0x00000300
|
|
#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_I2C3_TX_DMA_CHN 0x00030000
|
|
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* QUADSPI attributes.*/
|
|
#define STM32_HAS_QUADSPI1 TRUE
|
|
#define STM32_QUADSPI1_HANDLER Vector1B0
|
|
#define STM32_QUADSPI1_NUMBER 92
|
|
#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
|
|
#define STM32_QUADSPI1_DMA_CHN 0x30000000
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 2
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO TRUE
|
|
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 6))
|
|
#define STM32_SDC_SDIO_DMA_CHN 0x04004000
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2))
|
|
#define STM32_SPI1_RX_DMA_CHN 0x00000303
|
|
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_SPI1_TX_DMA_CHN 0x00303000
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI2_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
|
|
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI3 TRUE
|
|
#define STM32_SPI3_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
|
|
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 2))
|
|
#define STM32_SPI3_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7))
|
|
#define STM32_SPI3_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI4 TRUE
|
|
#define STM32_SPI4_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3))
|
|
#define STM32_SPI4_RX_DMA_CHN 0x00005004
|
|
#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_SPI4_TX_DMA_CHN 0x00050040
|
|
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM4 TRUE
|
|
#define STM32_TIM4_IS_32BITS FALSE
|
|
#define STM32_TIM4_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM5 TRUE
|
|
#define STM32_TIM5_IS_32BITS TRUE
|
|
#define STM32_TIM5_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM7 TRUE
|
|
#define STM32_TIM7_IS_32BITS FALSE
|
|
#define STM32_TIM7_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM8 TRUE
|
|
#define STM32_TIM8_IS_32BITS FALSE
|
|
#define STM32_TIM8_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM9 TRUE
|
|
#define STM32_TIM9_IS_32BITS FALSE
|
|
#define STM32_TIM9_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM10 TRUE
|
|
#define STM32_TIM10_IS_32BITS FALSE
|
|
#define STM32_TIM10_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM11 TRUE
|
|
#define STM32_TIM11_IS_32BITS FALSE
|
|
#define STM32_TIM11_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM12 TRUE
|
|
#define STM32_TIM12_IS_32BITS FALSE
|
|
#define STM32_TIM12_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM13 TRUE
|
|
#define STM32_TIM13_IS_32BITS FALSE
|
|
#define STM32_TIM13_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM14 TRUE
|
|
#define STM32_TIM14_IS_32BITS FALSE
|
|
#define STM32_TIM14_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM15 FALSE
|
|
#define STM32_HAS_TIM16 FALSE
|
|
#define STM32_HAS_TIM17 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00400400
|
|
#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
|
|
#define STM32_USART1_TX_DMA_CHN 0x40000000
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
|
#define STM32_USART2_RX_DMA_CHN 0x00400000
|
|
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
|
#define STM32_USART2_TX_DMA_CHN 0x04000000
|
|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
|
|
#define STM32_USART3_RX_DMA_CHN 0x00000040
|
|
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART3_TX_DMA_CHN 0x00074000
|
|
|
|
#define STM32_HAS_UART4 TRUE
|
|
#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_UART4_RX_DMA_CHN 0x00000400
|
|
#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_UART4_TX_DMA_CHN 0x00040000
|
|
|
|
#define STM32_HAS_UART5 TRUE
|
|
#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
|
|
#define STM32_UART5_RX_DMA_CHN 0x00000004
|
|
#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_UART5_TX_DMA_CHN 0x40000000
|
|
|
|
#define STM32_HAS_USART6 TRUE
|
|
#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2))
|
|
#define STM32_USART6_RX_DMA_CHN 0x00000550
|
|
#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 7))
|
|
#define STM32_USART6_TX_DMA_CHN 0x55000000
|
|
|
|
#define STM32_HAS_UART7 FALSE
|
|
#define STM32_HAS_UART8 FALSE
|
|
#define STM32_HAS_LPUART1 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_OTG_STEPPING 2
|
|
#define STM32_HAS_OTG1 TRUE
|
|
#define STM32_OTG1_ENDPOINTS 5
|
|
#define STM32_HAS_OTG2 TRUE
|
|
#define STM32_OTG2_ENDPOINTS 7
|
|
|
|
#define STM32_HAS_USB FALSE
|
|
|
|
/* IWDG attributes.*/
|
|
#define STM32_HAS_IWDG TRUE
|
|
#define STM32_IWDG_IS_WINDOWED FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC TRUE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D TRUE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC TRUE
|
|
#define STM32_FSMC_IS_FMC TRUE
|
|
#define STM32_FSMC_HANDLER Vector100
|
|
#define STM32_FSMC_NUMBER 48
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE FALSE
|
|
|
|
#endif /* defined(STM32F446xx) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F439xx, STM32F429xx, STM32F437xx, STM32F427xx. */
|
|
/*===========================================================================*/
|
|
|
|
#if defined(STM32F429_439xx) || defined(STM32F427_437xx)
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_ADC_HANDLER Vector88
|
|
#define STM32_ADC_NUMBER 18
|
|
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_ADC1_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_ADC2 TRUE
|
|
#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3))
|
|
#define STM32_ADC2_DMA_CHN 0x00001100
|
|
|
|
#define STM32_HAS_ADC3 TRUE
|
|
#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 1))
|
|
#define STM32_ADC3_DMA_CHN 0x00000022
|
|
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 TRUE
|
|
#define STM32_HAS_CAN3 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 28
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
|
#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_DAC1_CH1_DMA_CHN 0x00700000
|
|
|
|
#define STM32_HAS_DAC1_CH2 TRUE
|
|
#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_DAC1_CH2_DMA_CHN 0x07000000
|
|
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_CACHE_HANDLING FALSE
|
|
|
|
#define STM32_HAS_DMA1 TRUE
|
|
#define STM32_DMA1_CH0_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_HANDLER Vector70
|
|
#define STM32_DMA1_CH2_HANDLER Vector74
|
|
#define STM32_DMA1_CH3_HANDLER Vector78
|
|
#define STM32_DMA1_CH4_HANDLER Vector7C
|
|
#define STM32_DMA1_CH5_HANDLER Vector80
|
|
#define STM32_DMA1_CH6_HANDLER Vector84
|
|
#define STM32_DMA1_CH7_HANDLER VectorFC
|
|
#define STM32_DMA1_CH0_NUMBER 11
|
|
#define STM32_DMA1_CH1_NUMBER 12
|
|
#define STM32_DMA1_CH2_NUMBER 13
|
|
#define STM32_DMA1_CH3_NUMBER 14
|
|
#define STM32_DMA1_CH4_NUMBER 15
|
|
#define STM32_DMA1_CH5_NUMBER 16
|
|
#define STM32_DMA1_CH6_NUMBER 17
|
|
#define STM32_DMA1_CH7_NUMBER 47
|
|
|
|
#define STM32_HAS_DMA2 TRUE
|
|
#define STM32_DMA2_CH0_HANDLER Vector120
|
|
#define STM32_DMA2_CH1_HANDLER Vector124
|
|
#define STM32_DMA2_CH2_HANDLER Vector128
|
|
#define STM32_DMA2_CH3_HANDLER Vector12C
|
|
#define STM32_DMA2_CH4_HANDLER Vector130
|
|
#define STM32_DMA2_CH5_HANDLER Vector150
|
|
#define STM32_DMA2_CH6_HANDLER Vector154
|
|
#define STM32_DMA2_CH7_HANDLER Vector158
|
|
#define STM32_DMA2_CH0_NUMBER 56
|
|
#define STM32_DMA2_CH1_NUMBER 57
|
|
#define STM32_DMA2_CH2_NUMBER 58
|
|
#define STM32_DMA2_CH3_NUMBER 59
|
|
#define STM32_DMA2_CH4_NUMBER 60
|
|
#define STM32_DMA2_CH5_NUMBER 68
|
|
#define STM32_DMA2_CH6_NUMBER 69
|
|
#define STM32_DMA2_CH7_NUMBER 70
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH TRUE
|
|
#define STM32_ETH_HANDLER Vector134
|
|
#define STM32_ETH_NUMBER 61
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 23
|
|
#define STM32_EXTI_IMR_MASK 0x00000000U
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE TRUE
|
|
#define STM32_HAS_GPIOH TRUE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG TRUE
|
|
#define STM32_HAS_GPIOI TRUE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
|
|
RCC_AHB1ENR_GPIOBEN | \
|
|
RCC_AHB1ENR_GPIOCEN | \
|
|
RCC_AHB1ENR_GPIODEN | \
|
|
RCC_AHB1ENR_GPIOEEN | \
|
|
RCC_AHB1ENR_GPIOFEN | \
|
|
RCC_AHB1ENR_GPIOGEN | \
|
|
RCC_AHB1ENR_GPIOHEN | \
|
|
RCC_AHB1ENR_GPIOIEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_I2C1_RX_DMA_CHN 0x00100001
|
|
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_I2C1_TX_DMA_CHN 0x11000000
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3))
|
|
#define STM32_I2C2_RX_DMA_CHN 0x00007700
|
|
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_I2C2_TX_DMA_CHN 0x70000000
|
|
|
|
#define STM32_HAS_I2C3 TRUE
|
|
#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_I2C3_RX_DMA_CHN 0x00000300
|
|
#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_I2C3_TX_DMA_CHN 0x00030000
|
|
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* QUADSPI attributes.*/
|
|
#define STM32_HAS_QUADSPI1 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 2
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO TRUE
|
|
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 6))
|
|
#define STM32_SDC_SDIO_DMA_CHN 0x04004000
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2))
|
|
#define STM32_SPI1_RX_DMA_CHN 0x00000303
|
|
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_SPI1_TX_DMA_CHN 0x00303000
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI2_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
|
|
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI3 TRUE
|
|
#define STM32_SPI3_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
|
|
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 2))
|
|
#define STM32_SPI3_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7))
|
|
#define STM32_SPI3_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI4 TRUE
|
|
#define STM32_SPI4_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3))
|
|
#define STM32_SPI4_RX_DMA_CHN 0x00005004
|
|
#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_SPI4_TX_DMA_CHN 0x00050040
|
|
|
|
#define STM32_HAS_SPI5 TRUE
|
|
#define STM32_SPI5_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_SPI5_RX_DMA_CHN 0x00702000
|
|
#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) | \
|
|
STM32_DMA_STREAM_ID_MSK(2, 6))
|
|
#define STM32_SPI5_TX_DMA_CHN 0x07020000
|
|
|
|
#define STM32_HAS_SPI6 TRUE
|
|
#define STM32_SPI6_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6))
|
|
#define STM32_SPI6_RX_DMA_CHN 0x01000000
|
|
#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_SPI6_TX_DMA_CHN 0x00100000
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM4 TRUE
|
|
#define STM32_TIM4_IS_32BITS FALSE
|
|
#define STM32_TIM4_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM5 TRUE
|
|
#define STM32_TIM5_IS_32BITS TRUE
|
|
#define STM32_TIM5_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM7 TRUE
|
|
#define STM32_TIM7_IS_32BITS FALSE
|
|
#define STM32_TIM7_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM8 TRUE
|
|
#define STM32_TIM8_IS_32BITS FALSE
|
|
#define STM32_TIM8_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM9 TRUE
|
|
#define STM32_TIM9_IS_32BITS FALSE
|
|
#define STM32_TIM9_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM10 TRUE
|
|
#define STM32_TIM10_IS_32BITS FALSE
|
|
#define STM32_TIM10_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM11 TRUE
|
|
#define STM32_TIM11_IS_32BITS FALSE
|
|
#define STM32_TIM11_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM12 TRUE
|
|
#define STM32_TIM12_IS_32BITS FALSE
|
|
#define STM32_TIM12_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM13 TRUE
|
|
#define STM32_TIM13_IS_32BITS FALSE
|
|
#define STM32_TIM13_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM14 TRUE
|
|
#define STM32_TIM14_IS_32BITS FALSE
|
|
#define STM32_TIM14_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM15 FALSE
|
|
#define STM32_HAS_TIM16 FALSE
|
|
#define STM32_HAS_TIM17 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00400400
|
|
#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
|
|
#define STM32_USART1_TX_DMA_CHN 0x40000000
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
|
#define STM32_USART2_RX_DMA_CHN 0x00400000
|
|
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
|
#define STM32_USART2_TX_DMA_CHN 0x04000000
|
|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
|
|
#define STM32_USART3_RX_DMA_CHN 0x00000040
|
|
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART3_TX_DMA_CHN 0x00074000
|
|
|
|
#define STM32_HAS_UART4 TRUE
|
|
#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_UART4_RX_DMA_CHN 0x00000400
|
|
#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_UART4_TX_DMA_CHN 0x00040000
|
|
|
|
#define STM32_HAS_UART5 TRUE
|
|
#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
|
|
#define STM32_UART5_RX_DMA_CHN 0x00000004
|
|
#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_UART5_TX_DMA_CHN 0x40000000
|
|
|
|
#define STM32_HAS_USART6 TRUE
|
|
#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2))
|
|
#define STM32_USART6_RX_DMA_CHN 0x00000550
|
|
#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 7))
|
|
#define STM32_USART6_TX_DMA_CHN 0x55000000
|
|
|
|
#define STM32_HAS_UART7 TRUE
|
|
#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_UART7_RX_DMA_CHN 0x00005000
|
|
#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
|
|
#define STM32_UART7_TX_DMA_CHN 0x00000050
|
|
|
|
#define STM32_HAS_UART8 TRUE
|
|
#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
|
#define STM32_UART8_RX_DMA_CHN 0x05000000
|
|
#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
|
|
#define STM32_UART8_TX_DMA_CHN 0x00000005
|
|
|
|
#define STM32_HAS_LPUART1 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_OTG_STEPPING 1
|
|
#define STM32_HAS_OTG1 TRUE
|
|
#define STM32_OTG1_ENDPOINTS 3
|
|
#define STM32_HAS_OTG2 TRUE
|
|
#define STM32_OTG2_ENDPOINTS 5
|
|
|
|
#define STM32_HAS_USB FALSE
|
|
|
|
/* IWDG attributes.*/
|
|
#define STM32_HAS_IWDG TRUE
|
|
#define STM32_IWDG_IS_WINDOWED FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC TRUE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D TRUE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC TRUE
|
|
#define STM32_FSMC_IS_FMC TRUE
|
|
#define STM32_FSMC_HANDLER Vector100
|
|
#define STM32_FSMC_NUMBER 48
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE FALSE
|
|
|
|
#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F412Cx, STM32F412Rx, STM32F412Vx, STM32F412Zx */
|
|
/*===========================================================================*/
|
|
|
|
#if defined(STM32F412xx)
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_ADC_HANDLER Vector88
|
|
#define STM32_ADC_NUMBER 18
|
|
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_ADC1_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_ADC2 FALSE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 TRUE
|
|
#define STM32_HAS_CAN3 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 28
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 FALSE
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_CACHE_HANDLING FALSE
|
|
|
|
#define STM32_HAS_DMA1 TRUE
|
|
#define STM32_DMA1_CH0_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_HANDLER Vector70
|
|
#define STM32_DMA1_CH2_HANDLER Vector74
|
|
#define STM32_DMA1_CH3_HANDLER Vector78
|
|
#define STM32_DMA1_CH4_HANDLER Vector7C
|
|
#define STM32_DMA1_CH5_HANDLER Vector80
|
|
#define STM32_DMA1_CH6_HANDLER Vector84
|
|
#define STM32_DMA1_CH7_HANDLER VectorFC
|
|
#define STM32_DMA1_CH0_NUMBER 11
|
|
#define STM32_DMA1_CH1_NUMBER 12
|
|
#define STM32_DMA1_CH2_NUMBER 13
|
|
#define STM32_DMA1_CH3_NUMBER 14
|
|
#define STM32_DMA1_CH4_NUMBER 15
|
|
#define STM32_DMA1_CH5_NUMBER 16
|
|
#define STM32_DMA1_CH6_NUMBER 17
|
|
#define STM32_DMA1_CH7_NUMBER 47
|
|
|
|
#define STM32_HAS_DMA2 TRUE
|
|
#define STM32_DMA2_CH0_HANDLER Vector120
|
|
#define STM32_DMA2_CH1_HANDLER Vector124
|
|
#define STM32_DMA2_CH2_HANDLER Vector128
|
|
#define STM32_DMA2_CH3_HANDLER Vector12C
|
|
#define STM32_DMA2_CH4_HANDLER Vector130
|
|
#define STM32_DMA2_CH5_HANDLER Vector150
|
|
#define STM32_DMA2_CH6_HANDLER Vector154
|
|
#define STM32_DMA2_CH7_HANDLER Vector158
|
|
#define STM32_DMA2_CH0_NUMBER 56
|
|
#define STM32_DMA2_CH1_NUMBER 57
|
|
#define STM32_DMA2_CH2_NUMBER 58
|
|
#define STM32_DMA2_CH3_NUMBER 59
|
|
#define STM32_DMA2_CH4_NUMBER 60
|
|
#define STM32_DMA2_CH5_NUMBER 68
|
|
#define STM32_DMA2_CH6_NUMBER 69
|
|
#define STM32_DMA2_CH7_NUMBER 70
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 23
|
|
#define STM32_EXTI_IMR_MASK 0x00000000U
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE TRUE
|
|
#define STM32_HAS_GPIOH TRUE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG TRUE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
|
|
RCC_AHB1ENR_GPIOBEN | \
|
|
RCC_AHB1ENR_GPIOCEN | \
|
|
RCC_AHB1ENR_GPIODEN | \
|
|
RCC_AHB1ENR_GPIOEEN | \
|
|
RCC_AHB1ENR_GPIOFEN | \
|
|
RCC_AHB1ENR_GPIOGEN | \
|
|
RCC_AHB1ENR_GPIOHEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_I2C1_RX_DMA_CHN 0x00100001
|
|
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_I2C1_TX_DMA_CHN 0x11000000
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3))
|
|
#define STM32_I2C2_RX_DMA_CHN 0x00007700
|
|
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_I2C2_TX_DMA_CHN 0x70000000
|
|
|
|
#define STM32_HAS_I2C3 TRUE
|
|
#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_I2C3_RX_DMA_CHN 0x00000300
|
|
#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_I2C3_TX_DMA_CHN 0x00030000
|
|
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* QUADSPI attributes.*/
|
|
#define STM32_HAS_QUADSPI1 TRUE
|
|
#define STM32_QUADSPI1_HANDLER Vector1B0
|
|
#define STM32_QUADSPI1_NUMBER 92
|
|
#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
|
|
#define STM32_QUADSPI1_DMA_CHN 0x30000000
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 2
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO TRUE
|
|
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 6))
|
|
#define STM32_SDC_SDIO_DMA_CHN 0x04004000
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2))
|
|
#define STM32_SPI1_RX_DMA_CHN 0x00000303
|
|
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_SPI1_TX_DMA_CHN 0x00303000
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI2_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
|
|
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI3 TRUE
|
|
#define STM32_SPI3_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
|
|
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 2))
|
|
#define STM32_SPI3_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7))
|
|
#define STM32_SPI3_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI4 TRUE
|
|
#define STM32_SPI4_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_SPI4_RX_DMA_CHN 0x00045004
|
|
#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_SPI4_TX_DMA_CHN 0x00050040
|
|
|
|
#define STM32_HAS_SPI5 TRUE
|
|
#define STM32_SPI5_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_SPI5_RX_DMA_CHN 0x00702000
|
|
#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 6))
|
|
#define STM32_SPI5_TX_DMA_CHN 0x07520000
|
|
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM4 TRUE
|
|
#define STM32_TIM4_IS_32BITS FALSE
|
|
#define STM32_TIM4_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM5 TRUE
|
|
#define STM32_TIM5_IS_32BITS TRUE
|
|
#define STM32_TIM5_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM7 TRUE
|
|
#define STM32_TIM7_IS_32BITS FALSE
|
|
#define STM32_TIM7_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM9 TRUE
|
|
#define STM32_TIM9_IS_32BITS FALSE
|
|
#define STM32_TIM9_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM10 TRUE
|
|
#define STM32_TIM10_IS_32BITS FALSE
|
|
#define STM32_TIM10_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM11 TRUE
|
|
#define STM32_TIM11_IS_32BITS FALSE
|
|
#define STM32_TIM11_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM12 TRUE
|
|
#define STM32_TIM12_IS_32BITS FALSE
|
|
#define STM32_TIM12_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM13 TRUE
|
|
#define STM32_TIM13_IS_32BITS FALSE
|
|
#define STM32_TIM13_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM14 TRUE
|
|
#define STM32_TIM14_IS_32BITS FALSE
|
|
#define STM32_TIM14_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM15 FALSE
|
|
#define STM32_HAS_TIM16 FALSE
|
|
#define STM32_HAS_TIM17 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00400400
|
|
#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
|
|
#define STM32_USART1_TX_DMA_CHN 0x40000000
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
|
#define STM32_USART2_RX_DMA_CHN 0x00400000
|
|
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
|
#define STM32_USART2_TX_DMA_CHN 0x04000000
|
|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)
|
|
#define STM32_USART3_RX_DMA_CHN 0x00000040
|
|
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART3_TX_DMA_CHN 0x00074000
|
|
|
|
#define STM32_HAS_USART6 TRUE
|
|
#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2))
|
|
#define STM32_USART6_RX_DMA_CHN 0x00000550
|
|
#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 7))
|
|
#define STM32_USART6_TX_DMA_CHN 0x55000000
|
|
|
|
#define STM32_HAS_UART4 FALSE
|
|
#define STM32_HAS_UART5 FALSE
|
|
#define STM32_HAS_UART7 FALSE
|
|
#define STM32_HAS_UART8 FALSE
|
|
#define STM32_HAS_LPUART1 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_OTG_STEPPING 2
|
|
#define STM32_HAS_OTG1 TRUE
|
|
#define STM32_OTG1_ENDPOINTS 3
|
|
|
|
#define STM32_HAS_OTG2 FALSE
|
|
#define STM32_HAS_USB FALSE
|
|
|
|
/* IWDG attributes.*/
|
|
#define STM32_HAS_IWDG TRUE
|
|
#define STM32_IWDG_IS_WINDOWED FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE FALSE
|
|
|
|
#endif /* defined(STM32F412xx) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F411xC, STM32F411xE */
|
|
/*===========================================================================*/
|
|
|
|
#if defined(STM32F411xx)
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_ADC_HANDLER Vector88
|
|
#define STM32_ADC_NUMBER 18
|
|
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_ADC1_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_ADC2 FALSE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 FALSE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
#define STM32_HAS_CAN3 FALSE
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 FALSE
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_CACHE_HANDLING FALSE
|
|
|
|
#define STM32_HAS_DMA1 TRUE
|
|
#define STM32_DMA1_CH0_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_HANDLER Vector70
|
|
#define STM32_DMA1_CH2_HANDLER Vector74
|
|
#define STM32_DMA1_CH3_HANDLER Vector78
|
|
#define STM32_DMA1_CH4_HANDLER Vector7C
|
|
#define STM32_DMA1_CH5_HANDLER Vector80
|
|
#define STM32_DMA1_CH6_HANDLER Vector84
|
|
#define STM32_DMA1_CH7_HANDLER VectorFC
|
|
#define STM32_DMA1_CH0_NUMBER 11
|
|
#define STM32_DMA1_CH1_NUMBER 12
|
|
#define STM32_DMA1_CH2_NUMBER 13
|
|
#define STM32_DMA1_CH3_NUMBER 14
|
|
#define STM32_DMA1_CH4_NUMBER 15
|
|
#define STM32_DMA1_CH5_NUMBER 16
|
|
#define STM32_DMA1_CH6_NUMBER 17
|
|
#define STM32_DMA1_CH7_NUMBER 47
|
|
|
|
#define STM32_HAS_DMA2 TRUE
|
|
#define STM32_DMA2_CH0_HANDLER Vector120
|
|
#define STM32_DMA2_CH1_HANDLER Vector124
|
|
#define STM32_DMA2_CH2_HANDLER Vector128
|
|
#define STM32_DMA2_CH3_HANDLER Vector12C
|
|
#define STM32_DMA2_CH4_HANDLER Vector130
|
|
#define STM32_DMA2_CH5_HANDLER Vector150
|
|
#define STM32_DMA2_CH6_HANDLER Vector154
|
|
#define STM32_DMA2_CH7_HANDLER Vector158
|
|
#define STM32_DMA2_CH0_NUMBER 56
|
|
#define STM32_DMA2_CH1_NUMBER 57
|
|
#define STM32_DMA2_CH2_NUMBER 58
|
|
#define STM32_DMA2_CH3_NUMBER 59
|
|
#define STM32_DMA2_CH4_NUMBER 60
|
|
#define STM32_DMA2_CH5_NUMBER 68
|
|
#define STM32_DMA2_CH6_NUMBER 69
|
|
#define STM32_DMA2_CH7_NUMBER 70
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 23
|
|
#define STM32_EXTI_IMR_MASK 0x00000000U
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE TRUE
|
|
#define STM32_HAS_GPIOH TRUE
|
|
#define STM32_HAS_GPIOF FALSE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
|
|
RCC_AHB1ENR_GPIOBEN | \
|
|
RCC_AHB1ENR_GPIOCEN | \
|
|
RCC_AHB1ENR_GPIODEN | \
|
|
RCC_AHB1ENR_GPIOEEN | \
|
|
RCC_AHB1ENR_GPIOHEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_I2C1_RX_DMA_CHN 0x00100001
|
|
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 1))
|
|
#define STM32_I2C1_TX_DMA_CHN 0x11000000
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3))
|
|
#define STM32_I2C2_RX_DMA_CHN 0x00007700
|
|
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_I2C2_TX_DMA_CHN 0x70000000
|
|
|
|
#define STM32_HAS_I2C3 TRUE
|
|
#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
+ STM32_DMA_STREAM_ID_MSK(1, 2))
|
|
#define STM32_I2C3_RX_DMA_CHN 0x00000310
|
|
#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
+ STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_I2C3_TX_DMA_CHN 0x00630000
|
|
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* QUADSPI attributes.*/
|
|
#define STM32_HAS_QUADSPI1 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 2
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO TRUE
|
|
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 6))
|
|
#define STM32_SDC_SDIO_DMA_CHN 0x04004000
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2))
|
|
#define STM32_SPI1_RX_DMA_CHN 0x00000303
|
|
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_SPI1_TX_DMA_CHN 0x00303000
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI2_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
|
|
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI3 TRUE
|
|
#define STM32_SPI3_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
|
|
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 2))
|
|
#define STM32_SPI3_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7))
|
|
#define STM32_SPI3_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI4 TRUE
|
|
#define STM32_SPI4_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3))
|
|
#define STM32_SPI4_RX_DMA_CHN 0x00005004
|
|
#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_SPI4_TX_DMA_CHN 0x00050040
|
|
|
|
#define STM32_HAS_SPI5 TRUE
|
|
#define STM32_SPI5_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_SPI5_RX_DMA_CHN 0x00702000
|
|
#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 6))
|
|
#define STM32_SPI5_TX_DMA_CHN 0x07020000
|
|
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM4 TRUE
|
|
#define STM32_TIM4_IS_32BITS FALSE
|
|
#define STM32_TIM4_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM5 TRUE
|
|
#define STM32_TIM5_IS_32BITS TRUE
|
|
#define STM32_TIM5_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM9 TRUE
|
|
#define STM32_TIM9_IS_32BITS FALSE
|
|
#define STM32_TIM9_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM10 TRUE
|
|
#define STM32_TIM10_IS_32BITS FALSE
|
|
#define STM32_TIM10_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM11 TRUE
|
|
#define STM32_TIM11_IS_32BITS FALSE
|
|
#define STM32_TIM11_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM6 FALSE
|
|
#define STM32_HAS_TIM7 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM14 FALSE
|
|
#define STM32_HAS_TIM15 FALSE
|
|
#define STM32_HAS_TIM16 FALSE
|
|
#define STM32_HAS_TIM17 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00400400
|
|
#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
|
|
#define STM32_USART1_TX_DMA_CHN 0x40000000
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
|
#define STM32_USART2_RX_DMA_CHN 0x00400000
|
|
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
|
#define STM32_USART2_TX_DMA_CHN 0x04000000
|
|
|
|
#define STM32_HAS_USART3 FALSE
|
|
#define STM32_HAS_UART4 FALSE
|
|
#define STM32_HAS_UART5 FALSE
|
|
|
|
#define STM32_HAS_USART6 TRUE
|
|
#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2))
|
|
#define STM32_USART6_RX_DMA_CHN 0x00000550
|
|
#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 7))
|
|
#define STM32_USART6_TX_DMA_CHN 0x55000000
|
|
|
|
#define STM32_HAS_UART7 FALSE
|
|
#define STM32_HAS_UART8 FALSE
|
|
#define STM32_HAS_LPUART1 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_OTG_STEPPING 1
|
|
#define STM32_HAS_OTG1 TRUE
|
|
#define STM32_OTG1_ENDPOINTS 3
|
|
|
|
#define STM32_HAS_OTG2 FALSE
|
|
#define STM32_HAS_USB FALSE
|
|
|
|
/* IWDG attributes.*/
|
|
#define STM32_HAS_IWDG TRUE
|
|
#define STM32_IWDG_IS_WINDOWED FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE FALSE
|
|
|
|
#endif /* defined(STM32F411xx) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F410Cx, STM32F410Rx. */
|
|
/*===========================================================================*/
|
|
|
|
#if defined(STM32F410xx)
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_ADC_HANDLER Vector88
|
|
#define STM32_ADC_NUMBER 18
|
|
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_ADC1_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_ADC2 FALSE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 FALSE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
#define STM32_HAS_CAN3 FALSE
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
|
#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_DAC1_CH1_DMA_CHN 0x00700000
|
|
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_CACHE_HANDLING FALSE
|
|
|
|
#define STM32_HAS_DMA1 TRUE
|
|
#define STM32_DMA1_CH0_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_HANDLER Vector70
|
|
#define STM32_DMA1_CH2_HANDLER Vector74
|
|
#define STM32_DMA1_CH3_HANDLER Vector78
|
|
#define STM32_DMA1_CH4_HANDLER Vector7C
|
|
#define STM32_DMA1_CH5_HANDLER Vector80
|
|
#define STM32_DMA1_CH6_HANDLER Vector84
|
|
#define STM32_DMA1_CH7_HANDLER VectorFC
|
|
#define STM32_DMA1_CH0_NUMBER 11
|
|
#define STM32_DMA1_CH1_NUMBER 12
|
|
#define STM32_DMA1_CH2_NUMBER 13
|
|
#define STM32_DMA1_CH3_NUMBER 14
|
|
#define STM32_DMA1_CH4_NUMBER 15
|
|
#define STM32_DMA1_CH5_NUMBER 16
|
|
#define STM32_DMA1_CH6_NUMBER 17
|
|
#define STM32_DMA1_CH7_NUMBER 47
|
|
|
|
#define STM32_HAS_DMA2 TRUE
|
|
#define STM32_DMA2_CH0_HANDLER Vector120
|
|
#define STM32_DMA2_CH1_HANDLER Vector124
|
|
#define STM32_DMA2_CH2_HANDLER Vector128
|
|
#define STM32_DMA2_CH3_HANDLER Vector12C
|
|
#define STM32_DMA2_CH4_HANDLER Vector130
|
|
#define STM32_DMA2_CH5_HANDLER Vector150
|
|
#define STM32_DMA2_CH6_HANDLER Vector154
|
|
#define STM32_DMA2_CH7_HANDLER Vector158
|
|
#define STM32_DMA2_CH0_NUMBER 56
|
|
#define STM32_DMA2_CH1_NUMBER 57
|
|
#define STM32_DMA2_CH2_NUMBER 58
|
|
#define STM32_DMA2_CH3_NUMBER 59
|
|
#define STM32_DMA2_CH4_NUMBER 60
|
|
#define STM32_DMA2_CH5_NUMBER 68
|
|
#define STM32_DMA2_CH6_NUMBER 69
|
|
#define STM32_DMA2_CH7_NUMBER 70
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 23
|
|
#define STM32_EXTI_IMR_MASK 0x00000000U
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD FALSE
|
|
#define STM32_HAS_GPIOE FALSE
|
|
#define STM32_HAS_GPIOH TRUE
|
|
#define STM32_HAS_GPIOF FALSE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
|
|
RCC_AHB1ENR_GPIOBEN | \
|
|
RCC_AHB1ENR_GPIOCEN | \
|
|
RCC_AHB1ENR_GPIOHEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_I2C1_RX_DMA_CHN 0x00100001
|
|
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_I2C1_TX_DMA_CHN 0x11000000
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3))
|
|
#define STM32_I2C2_RX_DMA_CHN 0x00007700
|
|
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_I2C2_TX_DMA_CHN 0x70000000
|
|
|
|
#define STM32_HAS_I2C3 FALSE
|
|
|
|
#define STM32_HAS_I2C4 FALSE
|
|
#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3))
|
|
#define STM32_I2C4_RX_DMA_CHN 0x00002007
|
|
#define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 1))
|
|
#define STM32_I2C4_TX_DMA_CHN 0x00040020
|
|
|
|
/* QUADSPI attributes.*/
|
|
#define STM32_HAS_QUADSPI1 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 2
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2))
|
|
#define STM32_SPI1_RX_DMA_CHN 0x00000303
|
|
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3))
|
|
#define STM32_SPI1_TX_DMA_CHN 0x00003200
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI2_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
|
|
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI5 TRUE
|
|
#define STM32_SPI5_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_SPI5_RX_DMA_CHN 0x00702000
|
|
#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 6))
|
|
#define STM32_SPI5_TX_DMA_CHN 0x07020000
|
|
|
|
#define STM32_HAS_SPI3 FALSE
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM5 TRUE
|
|
#define STM32_TIM5_IS_32BITS TRUE
|
|
#define STM32_TIM5_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM9 TRUE
|
|
#define STM32_TIM9_IS_32BITS FALSE
|
|
#define STM32_TIM9_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM11 TRUE
|
|
#define STM32_TIM11_IS_32BITS FALSE
|
|
#define STM32_TIM11_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM2 FALSE
|
|
#define STM32_HAS_TIM3 FALSE
|
|
#define STM32_HAS_TIM4 FALSE
|
|
#define STM32_HAS_TIM7 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM14 FALSE
|
|
#define STM32_HAS_TIM15 FALSE
|
|
#define STM32_HAS_TIM16 FALSE
|
|
#define STM32_HAS_TIM17 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00400400
|
|
#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
|
|
#define STM32_USART1_TX_DMA_CHN 0x40000000
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7))
|
|
#define STM32_USART2_RX_DMA_CHN 0x60400000
|
|
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
|
#define STM32_USART2_TX_DMA_CHN 0x04000000
|
|
|
|
#define STM32_HAS_USART3 FALSE
|
|
#define STM32_HAS_UART4 FALSE
|
|
#define STM32_HAS_UART5 FALSE
|
|
|
|
#define STM32_HAS_USART6 TRUE
|
|
#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2))
|
|
#define STM32_USART6_RX_DMA_CHN 0x00000550
|
|
#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 7))
|
|
#define STM32_USART6_TX_DMA_CHN 0x55000000
|
|
|
|
#define STM32_HAS_UART7 FALSE
|
|
#define STM32_HAS_UART8 FALSE
|
|
#define STM32_HAS_LPUART1 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB FALSE
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* IWDG attributes.*/
|
|
#define STM32_HAS_IWDG TRUE
|
|
#define STM32_IWDG_IS_WINDOWED FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE FALSE
|
|
|
|
#endif /* defined(STM32F410xx) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F205xx */
|
|
/* STM32F215xx, STM32F207xx, STM32F217xx. */
|
|
/*===========================================================================*/
|
|
|
|
#if defined(STM32F40_41xxx) || defined(STM32F2XX)
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_ADC_HANDLER Vector88
|
|
#define STM32_ADC_NUMBER 18
|
|
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_ADC1_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_ADC2 TRUE
|
|
#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3))
|
|
#define STM32_ADC2_DMA_CHN 0x00001100
|
|
|
|
#define STM32_HAS_ADC3 TRUE
|
|
#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 1))
|
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#define STM32_ADC3_DMA_CHN 0x00000022
|
|
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 TRUE
|
|
#define STM32_HAS_CAN3 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 28
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
|
#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_DAC1_CH1_DMA_CHN 0x00700000
|
|
|
|
#define STM32_HAS_DAC1_CH2 TRUE
|
|
#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_DAC1_CH2_DMA_CHN 0x07000000
|
|
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_CACHE_HANDLING FALSE
|
|
|
|
#define STM32_HAS_DMA1 TRUE
|
|
#define STM32_DMA1_CH0_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_HANDLER Vector70
|
|
#define STM32_DMA1_CH2_HANDLER Vector74
|
|
#define STM32_DMA1_CH3_HANDLER Vector78
|
|
#define STM32_DMA1_CH4_HANDLER Vector7C
|
|
#define STM32_DMA1_CH5_HANDLER Vector80
|
|
#define STM32_DMA1_CH6_HANDLER Vector84
|
|
#define STM32_DMA1_CH7_HANDLER VectorFC
|
|
#define STM32_DMA1_CH0_NUMBER 11
|
|
#define STM32_DMA1_CH1_NUMBER 12
|
|
#define STM32_DMA1_CH2_NUMBER 13
|
|
#define STM32_DMA1_CH3_NUMBER 14
|
|
#define STM32_DMA1_CH4_NUMBER 15
|
|
#define STM32_DMA1_CH5_NUMBER 16
|
|
#define STM32_DMA1_CH6_NUMBER 17
|
|
#define STM32_DMA1_CH7_NUMBER 47
|
|
|
|
#define STM32_HAS_DMA2 TRUE
|
|
#define STM32_DMA2_CH0_HANDLER Vector120
|
|
#define STM32_DMA2_CH1_HANDLER Vector124
|
|
#define STM32_DMA2_CH2_HANDLER Vector128
|
|
#define STM32_DMA2_CH3_HANDLER Vector12C
|
|
#define STM32_DMA2_CH4_HANDLER Vector130
|
|
#define STM32_DMA2_CH5_HANDLER Vector150
|
|
#define STM32_DMA2_CH6_HANDLER Vector154
|
|
#define STM32_DMA2_CH7_HANDLER Vector158
|
|
#define STM32_DMA2_CH0_NUMBER 56
|
|
#define STM32_DMA2_CH1_NUMBER 57
|
|
#define STM32_DMA2_CH2_NUMBER 58
|
|
#define STM32_DMA2_CH3_NUMBER 59
|
|
#define STM32_DMA2_CH4_NUMBER 60
|
|
#define STM32_DMA2_CH5_NUMBER 68
|
|
#define STM32_DMA2_CH6_NUMBER 69
|
|
#define STM32_DMA2_CH7_NUMBER 70
|
|
|
|
/* ETH attributes.*/
|
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F205xx) || \
|
|
defined(STM32F215xx)
|
|
#define STM32_HAS_ETH FALSE
|
|
#else
|
|
#define STM32_HAS_ETH TRUE
|
|
#define STM32_ETH_HANDLER Vector134
|
|
#define STM32_ETH_NUMBER 61
|
|
#endif
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 23
|
|
#define STM32_EXTI_IMR_MASK 0x00000000U
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE TRUE
|
|
#define STM32_HAS_GPIOH TRUE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG TRUE
|
|
#define STM32_HAS_GPIOI TRUE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
|
|
RCC_AHB1ENR_GPIOBEN | \
|
|
RCC_AHB1ENR_GPIOCEN | \
|
|
RCC_AHB1ENR_GPIODEN | \
|
|
RCC_AHB1ENR_GPIOEEN | \
|
|
RCC_AHB1ENR_GPIOFEN | \
|
|
RCC_AHB1ENR_GPIOGEN | \
|
|
RCC_AHB1ENR_GPIOHEN | \
|
|
RCC_AHB1ENR_GPIOIEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_I2C1_RX_DMA_CHN 0x00100001
|
|
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_I2C1_TX_DMA_CHN 0x11000000
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3))
|
|
#define STM32_I2C2_RX_DMA_CHN 0x00007700
|
|
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_I2C2_TX_DMA_CHN 0x70000000
|
|
|
|
#define STM32_HAS_I2C3 TRUE
|
|
#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_I2C3_RX_DMA_CHN 0x00000300
|
|
#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_I2C3_TX_DMA_CHN 0x00030000
|
|
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* QUADSPI attributes.*/
|
|
#define STM32_HAS_QUADSPI1 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#if !defined(STM32F2XX)
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#else
|
|
#define STM32_RTC_HAS_SUBSECONDS FALSE
|
|
#endif
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 2
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO TRUE
|
|
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 6))
|
|
#define STM32_SDC_SDIO_DMA_CHN 0x04004000
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_SUPPORTS_I2S FALSE
|
|
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2))
|
|
#define STM32_SPI1_RX_DMA_CHN 0x00000303
|
|
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_SPI1_TX_DMA_CHN 0x00303000
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI2_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
|
|
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI3 TRUE
|
|
#define STM32_SPI3_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
|
|
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 2))
|
|
#define STM32_SPI3_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7))
|
|
#define STM32_SPI3_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM4 TRUE
|
|
#define STM32_TIM4_IS_32BITS FALSE
|
|
#define STM32_TIM4_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM5 TRUE
|
|
#define STM32_TIM5_IS_32BITS TRUE
|
|
#define STM32_TIM5_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM7 TRUE
|
|
#define STM32_TIM7_IS_32BITS FALSE
|
|
#define STM32_TIM7_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM8 TRUE
|
|
#define STM32_TIM8_IS_32BITS FALSE
|
|
#define STM32_TIM8_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM9 TRUE
|
|
#define STM32_TIM9_IS_32BITS FALSE
|
|
#define STM32_TIM9_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM10 TRUE
|
|
#define STM32_TIM10_IS_32BITS FALSE
|
|
#define STM32_TIM10_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM11 TRUE
|
|
#define STM32_TIM11_IS_32BITS FALSE
|
|
#define STM32_TIM11_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM12 TRUE
|
|
#define STM32_TIM12_IS_32BITS FALSE
|
|
#define STM32_TIM12_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM13 TRUE
|
|
#define STM32_TIM13_IS_32BITS FALSE
|
|
#define STM32_TIM13_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM14 TRUE
|
|
#define STM32_TIM14_IS_32BITS FALSE
|
|
#define STM32_TIM14_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM15 FALSE
|
|
#define STM32_HAS_TIM16 FALSE
|
|
#define STM32_HAS_TIM17 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00400400
|
|
#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
|
|
#define STM32_USART1_TX_DMA_CHN 0x40000000
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
|
#define STM32_USART2_RX_DMA_CHN 0x00400000
|
|
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
|
#define STM32_USART2_TX_DMA_CHN 0x04000000
|
|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
|
|
#define STM32_USART3_RX_DMA_CHN 0x00000040
|
|
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART3_TX_DMA_CHN 0x00074000
|
|
|
|
#define STM32_HAS_UART4 TRUE
|
|
#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_UART4_RX_DMA_CHN 0x00000400
|
|
#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_UART4_TX_DMA_CHN 0x00040000
|
|
|
|
#define STM32_HAS_UART5 TRUE
|
|
#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
|
|
#define STM32_UART5_RX_DMA_CHN 0x00000004
|
|
#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_UART5_TX_DMA_CHN 0x40000000
|
|
|
|
#define STM32_HAS_USART6 TRUE
|
|
#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2))
|
|
#define STM32_USART6_RX_DMA_CHN 0x00000550
|
|
#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 7))
|
|
#define STM32_USART6_TX_DMA_CHN 0x55000000
|
|
|
|
#define STM32_HAS_UART7 FALSE
|
|
#define STM32_HAS_UART8 FALSE
|
|
#define STM32_HAS_LPUART1 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_OTG_STEPPING 1
|
|
#define STM32_HAS_OTG1 TRUE
|
|
#define STM32_OTG1_ENDPOINTS 3
|
|
#define STM32_HAS_OTG2 TRUE
|
|
#define STM32_OTG2_ENDPOINTS 5
|
|
|
|
#define STM32_HAS_USB FALSE
|
|
|
|
/* IWDG attributes.*/
|
|
#define STM32_HAS_IWDG TRUE
|
|
#define STM32_IWDG_IS_WINDOWED FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC TRUE
|
|
#define STM32_FSMC_IS_FMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE FALSE
|
|
|
|
#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F401xx. */
|
|
/*===========================================================================*/
|
|
|
|
#if defined(STM32F401xx)
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_ADC_HANDLER Vector88
|
|
#define STM32_ADC_NUMBER 18
|
|
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_ADC1_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_ADC2 TRUE
|
|
#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3))
|
|
#define STM32_ADC2_DMA_CHN 0x00001100
|
|
|
|
#define STM32_HAS_ADC3 TRUE
|
|
#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 1))
|
|
#define STM32_ADC3_DMA_CHN 0x00000022
|
|
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 TRUE
|
|
#define STM32_HAS_CAN3 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 28
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 FALSE
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_CACHE_HANDLING FALSE
|
|
|
|
#define STM32_HAS_DMA1 TRUE
|
|
#define STM32_DMA1_CH0_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_HANDLER Vector70
|
|
#define STM32_DMA1_CH2_HANDLER Vector74
|
|
#define STM32_DMA1_CH3_HANDLER Vector78
|
|
#define STM32_DMA1_CH4_HANDLER Vector7C
|
|
#define STM32_DMA1_CH5_HANDLER Vector80
|
|
#define STM32_DMA1_CH6_HANDLER Vector84
|
|
#define STM32_DMA1_CH7_HANDLER VectorFC
|
|
#define STM32_DMA1_CH0_NUMBER 11
|
|
#define STM32_DMA1_CH1_NUMBER 12
|
|
#define STM32_DMA1_CH2_NUMBER 13
|
|
#define STM32_DMA1_CH3_NUMBER 14
|
|
#define STM32_DMA1_CH4_NUMBER 15
|
|
#define STM32_DMA1_CH5_NUMBER 16
|
|
#define STM32_DMA1_CH6_NUMBER 17
|
|
#define STM32_DMA1_CH7_NUMBER 47
|
|
|
|
#define STM32_HAS_DMA2 TRUE
|
|
#define STM32_DMA2_CH0_HANDLER Vector120
|
|
#define STM32_DMA2_CH1_HANDLER Vector124
|
|
#define STM32_DMA2_CH2_HANDLER Vector128
|
|
#define STM32_DMA2_CH3_HANDLER Vector12C
|
|
#define STM32_DMA2_CH4_HANDLER Vector130
|
|
#define STM32_DMA2_CH5_HANDLER Vector150
|
|
#define STM32_DMA2_CH6_HANDLER Vector154
|
|
#define STM32_DMA2_CH7_HANDLER Vector158
|
|
#define STM32_DMA2_CH0_NUMBER 56
|
|
#define STM32_DMA2_CH1_NUMBER 57
|
|
#define STM32_DMA2_CH2_NUMBER 58
|
|
#define STM32_DMA2_CH3_NUMBER 59
|
|
#define STM32_DMA2_CH4_NUMBER 60
|
|
#define STM32_DMA2_CH5_NUMBER 68
|
|
#define STM32_DMA2_CH6_NUMBER 69
|
|
#define STM32_DMA2_CH7_NUMBER 70
|
|
|
|
/* ETH attributes.*/
|
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_LINES 23
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#define STM32_EXTI_IMR_MASK 0x00000000U
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOH TRUE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
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RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | \
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RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
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STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C1_RX_DMA_CHN 0x00100001
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
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STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_I2C1_TX_DMA_CHN 0x11000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_I2C2_RX_DMA_CHN 0x00007700
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#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
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#define STM32_I2C2_TX_DMA_CHN 0x70000000
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#define STM32_HAS_I2C3 TRUE
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#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_I2C3_RX_DMA_CHN 0x00000300
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#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_I2C3_TX_DMA_CHN 0x00030000
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#define STM32_HAS_I2C4 FALSE
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/* QUADSPI attributes.*/
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#define STM32_HAS_QUADSPI1 FALSE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO TRUE
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#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_SDC_SDIO_DMA_CHN 0x04004000
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S FALSE
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#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 2))
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#define STM32_SPI1_RX_DMA_CHN 0x00000303
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#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_SPI1_TX_DMA_CHN 0x00303000
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_SUPPORTS_I2S TRUE
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#define STM32_SPI2_I2S_FULLDUPLEX TRUE
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#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_SPI2_RX_DMA_CHN 0x00000000
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#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_SPI2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_SUPPORTS_I2S TRUE
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#define STM32_SPI3_I2S_FULLDUPLEX TRUE
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#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
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STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_SPI3_RX_DMA_CHN 0x00000000
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#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
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STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_SPI3_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI4 TRUE
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#define STM32_SPI4_SUPPORTS_I2S FALSE
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#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_SPI4_RX_DMA_CHN 0x00005004
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#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_SPI4_TX_DMA_CHN 0x00050040
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 4
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_HAS_TIM5 TRUE
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#define STM32_TIM5_IS_32BITS TRUE
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#define STM32_TIM5_CHANNELS 4
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#define STM32_HAS_TIM9 TRUE
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#define STM32_TIM9_IS_32BITS FALSE
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#define STM32_TIM9_CHANNELS 2
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#define STM32_HAS_TIM10 TRUE
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#define STM32_TIM10_IS_32BITS FALSE
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#define STM32_TIM10_CHANNELS 1
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#define STM32_HAS_TIM11 TRUE
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#define STM32_TIM11_IS_32BITS FALSE
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#define STM32_TIM11_CHANNELS 1
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#define STM32_HAS_TIM6 FALSE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM16 FALSE
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#define STM32_HAS_TIM17 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_USART1_RX_DMA_CHN 0x00400400
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#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
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#define STM32_USART1_TX_DMA_CHN 0x40000000
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#define STM32_HAS_USART2 TRUE
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#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_USART2_RX_DMA_CHN 0x00400000
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#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
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#define STM32_USART2_TX_DMA_CHN 0x04000000
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#define STM32_HAS_USART3 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 TRUE
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#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 2))
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#define STM32_USART6_RX_DMA_CHN 0x00000550
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#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_USART6_TX_DMA_CHN 0x55000000
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#define STM32_HAS_UART7 FALSE
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#define STM32_HAS_UART8 FALSE
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#define STM32_HAS_LPUART1 FALSE
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/* USB attributes.*/
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#define STM32_OTG_STEPPING 1
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#define STM32_HAS_OTG1 TRUE
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#define STM32_OTG1_ENDPOINTS 3
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#define STM32_HAS_OTG2 FALSE
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#define STM32_HAS_USB FALSE
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/* IWDG attributes.*/
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#define STM32_HAS_IWDG TRUE
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#define STM32_IWDG_IS_WINDOWED FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE FALSE
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#endif /* defined(STM32F401xx) */
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/** @} */
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#endif /* STM32_REGISTRY_H */
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/** @} */
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