267 lines
8.0 KiB
C
Executable File
267 lines
8.0 KiB
C
Executable File
/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file USBv1/stm32_usb.h
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* @brief STM32 USB registers layout header.
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* @note This file requires definitions from the ST STM32 header files
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* stm32f10x.h or stm32l1xx.h.
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*
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* @addtogroup USB
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* @{
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*/
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#ifndef STM32_USB_H
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#define STM32_USB_H
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/**
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* @brief Number of the available endpoints.
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* @details This value does not include the endpoint 0 which is always present.
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*/
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#define USB_ENDOPOINTS_NUMBER 7
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/**
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* @brief Width of USB packet memory accesses.
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*/
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#if STM32_USB_ACCESS_SCHEME_2x16
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typedef uint16_t stm32_usb_pma_t;
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#else
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typedef uint32_t stm32_usb_pma_t;
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#endif
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/**
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* @brief USB registers block.
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*/
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typedef struct {
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/**
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* @brief Endpoint registers.
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*/
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volatile uint32_t EPR[USB_ENDOPOINTS_NUMBER + 1];
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/*
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* @brief Reserved space.
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*/
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volatile uint32_t _r20[8];
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/*
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* @brief Control Register.
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*/
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volatile uint32_t CNTR;
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/*
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* @brief Interrupt Status Register.
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*/
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volatile uint32_t ISTR;
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/*
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* @brief Frame Number Register.
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*/
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volatile uint32_t FNR;
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/*
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* @brief Device Address Register.
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*/
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volatile uint32_t DADDR;
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/*
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* @brief Buffer Table Address.
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*/
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volatile uint32_t BTABLE;
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/*
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* @brief LPM Control and Status Register.
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*/
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volatile uint32_t LPMCSR;
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#if STM32_USB_HAS_BCDR
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/*
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* @brief Battery Charging Detector
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*/
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volatile uint32_t BCDR;
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#endif
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} stm32_usb_t;
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/**
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* @brief USB descriptor registers block.
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*/
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typedef struct {
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/**
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* @brief TX buffer offset register.
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*/
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volatile stm32_usb_pma_t TXADDR0;
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/**
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* @brief TX counter register 0.
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*/
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volatile stm32_usb_pma_t TXCOUNT0;
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/**
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* @brief RX buffer offset register.
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*/
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volatile stm32_usb_pma_t RXADDR0;
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/**
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* @brief RX counter register 0.
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*/
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volatile stm32_usb_pma_t RXCOUNT0;
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} stm32_usb_descriptor_t;
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/**
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* @name Register aliases
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* @{
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*/
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#define RXCOUNT1 TXCOUNT0
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#define TXCOUNT1 RXCOUNT0
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#define RXADDR1 TXADDR0
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#define TXADDR1 RXADDR0
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/** @} */
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/**
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* @brief USB registers block numeric address.
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*/
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#if defined(USB_BASE) || defined(__DOXYGEN__)
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#define STM32_USB_BASE USB_BASE
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#else
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#define STM32_USB_BASE (APB1PERIPH_BASE + 0x5C00)
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#endif
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/**
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* @brief USB RAM numeric address.
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*/
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#if defined(USB_PMAADDR) || defined(__DOXYGEN__)
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#define STM32_USBRAM_BASE USB_PMAADDR
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#else
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#define STM32_USBRAM_BASE (APB1PERIPH_BASE + 0x6000)
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#endif
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/**
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* @brief Pointer to the USB registers block.
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*/
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#define STM32_USB ((stm32_usb_t *)STM32_USB_BASE)
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/**
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* @brief Pointer to the USB RAM.
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*/
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#define STM32_USBRAM ((stm32_usb_pma_t *)STM32_USBRAM_BASE)
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/**
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* @brief Mask of all the toggling bits in the EPR register.
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*/
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#define EPR_TOGGLE_MASK (EPR_STAT_TX_MASK | EPR_DTOG_TX | \
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EPR_STAT_RX_MASK | EPR_DTOG_RX | \
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EPR_SETUP)
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#define EPR_EA_MASK 0x000F
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#define EPR_STAT_TX_MASK 0x0030
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#define EPR_STAT_TX_DIS 0x0000
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#define EPR_STAT_TX_STALL 0x0010
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#define EPR_STAT_TX_NAK 0x0020
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#define EPR_STAT_TX_VALID 0x0030
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#define EPR_DTOG_TX 0x0040
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#define EPR_SWBUF_RX EPR_DTOG_TX
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#define EPR_CTR_TX 0x0080
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#define EPR_EP_KIND 0x0100
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#define EPR_EP_DBL_BUF EPR_EP_KIND
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#define EPR_EP_STATUS_OUT EPR_EP_KIND
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#define EPR_EP_TYPE_MASK 0x0600
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#define EPR_EP_TYPE_BULK 0x0000
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#define EPR_EP_TYPE_CONTROL 0x0200
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#define EPR_EP_TYPE_ISO 0x0400
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#define EPR_EP_TYPE_INTERRUPT 0x0600
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#define EPR_SETUP 0x0800
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#define EPR_STAT_RX_MASK 0x3000
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#define EPR_STAT_RX_DIS 0x0000
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#define EPR_STAT_RX_STALL 0x1000
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#define EPR_STAT_RX_NAK 0x2000
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#define EPR_STAT_RX_VALID 0x3000
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#define EPR_DTOG_RX 0x4000
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#define EPR_SWBUF_TX EPR_DTOG_RX
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#define EPR_CTR_RX 0x8000
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#define CNTR_FRES 0x0001
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#define CNTR_PDWN 0x0002
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#define CNTR_LP_MODE 0x0004
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#define CNTR_FSUSP 0x0008
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#define CNTR_RESUME 0x0010
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#define CNTR_ESOFM 0x0100
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#define CNTR_SOFM 0x0200
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#define CNTR_RESETM 0x0400
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#define CNTR_SUSPM 0x0800
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#define CNTR_WKUPM 0x1000
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#define CNTR_ERRM 0x2000
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#define CNTR_PMAOVRM 0x4000
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#define CNTR_CTRM 0x8000
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#define ISTR_EP_ID_MASK 0x000F
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#define ISTR_DIR 0x0010
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#define ISTR_ESOF 0x0100
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#define ISTR_SOF 0x0200
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#define ISTR_RESET 0x0400
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#define ISTR_SUSP 0x0800
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#define ISTR_WKUP 0x1000
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#define ISTR_ERR 0x2000
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#define ISTR_PMAOVR 0x4000
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#define ISTR_CTR 0x8000
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#define FNR_FN_MASK 0x07FF
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#define FNR_LSOF 0x1800
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#define FNR_LCK 0x2000
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#define FNR_RXDM 0x4000
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#define FNR_RXDP 0x8000
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#define DADDR_ADD_MASK 0x007F
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#define DADDR_EF 0x0080
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#define RXCOUNT_COUNT_MASK 0x03FF
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#define TXCOUNT_COUNT_MASK 0x03FF
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#define EPR_CTR_MASK (EPR_CTR_TX | EPR_CTR_RX)
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#define EPR_SET(ep, epr) \
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STM32_USB->EPR[ep] = ((epr) & ~EPR_TOGGLE_MASK) | EPR_CTR_MASK
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#define EPR_TOGGLE(ep, epr) \
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STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] ^ ((epr) & EPR_TOGGLE_MASK)) \
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| EPR_CTR_MASK
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#define EPR_SET_STAT_RX(ep, epr) \
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STM32_USB->EPR[ep] = ((STM32_USB->EPR[ep] & \
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~(EPR_TOGGLE_MASK & ~EPR_STAT_RX_MASK)) ^ \
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(epr)) | EPR_CTR_MASK
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#define EPR_SET_STAT_TX(ep, epr) \
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STM32_USB->EPR[ep] = ((STM32_USB->EPR[ep] & \
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~(EPR_TOGGLE_MASK & ~EPR_STAT_TX_MASK)) ^ \
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(epr)) | EPR_CTR_MASK
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#define EPR_CLEAR_CTR_RX(ep) \
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STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & ~EPR_CTR_RX & ~EPR_TOGGLE_MASK)\
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| EPR_CTR_TX
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#define EPR_CLEAR_CTR_TX(ep) \
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STM32_USB->EPR[ep] = (STM32_USB->EPR[ep] & ~EPR_CTR_TX & ~EPR_TOGGLE_MASK)\
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| EPR_CTR_RX
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/**
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* @brief Returns an endpoint descriptor pointer.
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*/
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#define USB_GET_DESCRIPTOR(ep) \
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((stm32_usb_descriptor_t *)((uint32_t)STM32_USBRAM_BASE + \
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(uint32_t)STM32_USB->BTABLE + \
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(uint32_t)(ep) * \
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sizeof(stm32_usb_descriptor_t)))
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/**
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* @brief Converts from a PMA address to a physical address.
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*/
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#define USB_ADDR2PTR(addr) \
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((stm32_usb_pma_t *)((addr) * \
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(sizeof(stm32_usb_pma_t) / 2) + \
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STM32_USBRAM_BASE))
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#endif /* STM32_USB_H */
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/** @} */
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