548 lines
17 KiB
C
Executable File
548 lines
17 KiB
C
Executable File
/*
|
|
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
|
|
|
Licensed under the Apache License, Version 2.0 (the "License");
|
|
you may not use this file except in compliance with the License.
|
|
You may obtain a copy of the License at
|
|
|
|
http://www.apache.org/licenses/LICENSE-2.0
|
|
|
|
Unless required by applicable law or agreed to in writing, software
|
|
distributed under the License is distributed on an "AS IS" BASIS,
|
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
See the License for the specific language governing permissions and
|
|
limitations under the License.
|
|
*/
|
|
|
|
/**
|
|
* @file SPIv2/hal_spi_lld.h
|
|
* @brief STM32 SPI subsystem low level driver header.
|
|
*
|
|
* @addtogroup SPI
|
|
* @{
|
|
*/
|
|
|
|
#ifndef HAL_SPI_LLD_H
|
|
#define HAL_SPI_LLD_H
|
|
|
|
#if HAL_USE_SPI || defined(__DOXYGEN__)
|
|
|
|
/*===========================================================================*/
|
|
/* Driver constants. */
|
|
/*===========================================================================*/
|
|
|
|
/*===========================================================================*/
|
|
/* Driver pre-compile time settings. */
|
|
/*===========================================================================*/
|
|
|
|
/**
|
|
* @name Configuration options
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief SPI1 driver enable switch.
|
|
* @details If set to @p TRUE the support for SPI1 is included.
|
|
* @note The default is @p FALSE.
|
|
*/
|
|
#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_USE_SPI1 FALSE
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI2 driver enable switch.
|
|
* @details If set to @p TRUE the support for SPI2 is included.
|
|
* @note The default is @p FALSE.
|
|
*/
|
|
#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_USE_SPI2 FALSE
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI3 driver enable switch.
|
|
* @details If set to @p TRUE the support for SPI3 is included.
|
|
* @note The default is @p FALSE.
|
|
*/
|
|
#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_USE_SPI3 FALSE
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI4 driver enable switch.
|
|
* @details If set to @p TRUE the support for SPI4 is included.
|
|
* @note The default is @p FALSE.
|
|
*/
|
|
#if !defined(STM32_SPI_USE_SPI4) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_USE_SPI4 FALSE
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI5 driver enable switch.
|
|
* @details If set to @p TRUE the support for SPI5 is included.
|
|
* @note The default is @p FALSE.
|
|
*/
|
|
#if !defined(STM32_SPI_USE_SPI5) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_USE_SPI5 FALSE
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI6 driver enable switch.
|
|
* @details If set to @p TRUE the support for SPI6 is included.
|
|
* @note The default is @p FALSE.
|
|
*/
|
|
#if !defined(STM32_SPI_USE_SPI6) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_USE_SPI6 FALSE
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI1 interrupt priority level setting.
|
|
*/
|
|
#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI2 interrupt priority level setting.
|
|
*/
|
|
#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI3 interrupt priority level setting.
|
|
*/
|
|
#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI4 interrupt priority level setting.
|
|
*/
|
|
#if !defined(STM32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI5 interrupt priority level setting.
|
|
*/
|
|
#if !defined(STM32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI6 interrupt priority level setting.
|
|
*/
|
|
#if !defined(STM32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI1 DMA priority (0..3|lowest..highest).
|
|
* @note The priority level is used for both the TX and RX DMA streams but
|
|
* because of the streams ordering the RX stream has always priority
|
|
* over the TX stream.
|
|
*/
|
|
#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI2 DMA priority (0..3|lowest..highest).
|
|
* @note The priority level is used for both the TX and RX DMA streams but
|
|
* because of the streams ordering the RX stream has always priority
|
|
* over the TX stream.
|
|
*/
|
|
#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI3 DMA priority (0..3|lowest..highest).
|
|
* @note The priority level is used for both the TX and RX DMA streams but
|
|
* because of the streams ordering the RX stream has always priority
|
|
* over the TX stream.
|
|
*/
|
|
#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI4 DMA priority (0..3|lowest..highest).
|
|
* @note The priority level is used for both the TX and RX DMA streams but
|
|
* because of the streams ordering the RX stream has always priority
|
|
* over the TX stream.
|
|
*/
|
|
#if !defined(STM32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_SPI4_DMA_PRIORITY 1
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI5 DMA priority (0..3|lowest..highest).
|
|
* @note The priority level is used for both the TX and RX DMA streams but
|
|
* because of the streams ordering the RX stream has always priority
|
|
* over the TX stream.
|
|
*/
|
|
#if !defined(STM32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_SPI5_DMA_PRIORITY 1
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI6 DMA priority (0..3|lowest..highest).
|
|
* @note The priority level is used for both the TX and RX DMA streams but
|
|
* because of the streams ordering the RX stream has always priority
|
|
* over the TX stream.
|
|
*/
|
|
#if !defined(STM32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_SPI6_DMA_PRIORITY 1
|
|
#endif
|
|
|
|
/**
|
|
* @brief SPI DMA error hook.
|
|
*/
|
|
#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
|
|
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
|
#endif
|
|
/** @} */
|
|
|
|
/*===========================================================================*/
|
|
/* Derived constants and error checks. */
|
|
/*===========================================================================*/
|
|
|
|
#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1
|
|
#error "SPI1 not present in the selected device"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2
|
|
#error "SPI2 not present in the selected device"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3
|
|
#error "SPI3 not present in the selected device"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI4 && !STM32_HAS_SPI4
|
|
#error "SPI4 not present in the selected device"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI5 && !STM32_HAS_SPI5
|
|
#error "SPI5 not present in the selected device"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI6 && !STM32_HAS_SPI6
|
|
#error "SPI6 not present in the selected device"
|
|
#endif
|
|
|
|
#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 && \
|
|
!STM32_SPI_USE_SPI4 && !STM32_SPI_USE_SPI5 && !STM32_SPI_USE_SPI6
|
|
#error "SPI driver activated but no SPI peripheral assigned"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI1 && \
|
|
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
|
|
#error "Invalid IRQ priority assigned to SPI1"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI2 && \
|
|
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
|
|
#error "Invalid IRQ priority assigned to SPI2"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI3 && \
|
|
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
|
|
#error "Invalid IRQ priority assigned to SPI3"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI4 && \
|
|
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY)
|
|
#error "Invalid IRQ priority assigned to SPI4"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI5 && \
|
|
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY)
|
|
#error "Invalid IRQ priority assigned to SPI5"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI6 && \
|
|
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY)
|
|
#error "Invalid IRQ priority assigned to SPI6"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI1 && \
|
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
|
|
#error "Invalid DMA priority assigned to SPI1"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI2 && \
|
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY)
|
|
#error "Invalid DMA priority assigned to SPI2"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI3 && \
|
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY)
|
|
#error "Invalid DMA priority assigned to SPI3"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI4 && \
|
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI4_DMA_PRIORITY)
|
|
#error "Invalid DMA priority assigned to SPI4"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI5 && \
|
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI5_DMA_PRIORITY)
|
|
#error "Invalid DMA priority assigned to SPI5"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI6 && \
|
|
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI6_DMA_PRIORITY)
|
|
#error "Invalid DMA priority assigned to SPI6"
|
|
#endif
|
|
|
|
/* The following checks are only required when there is a DMA able to
|
|
reassign streams to different channels.*/
|
|
#if STM32_ADVANCED_DMA
|
|
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
|
|
#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) || \
|
|
!defined(STM32_SPI_SPI1_TX_DMA_STREAM))
|
|
#error "SPI1 DMA streams not defined"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) || \
|
|
!defined(STM32_SPI_SPI2_TX_DMA_STREAM))
|
|
#error "SPI2 DMA streams not defined"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) || \
|
|
!defined(STM32_SPI_SPI3_TX_DMA_STREAM))
|
|
#error "SPI3 DMA streams not defined"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_STREAM) || \
|
|
!defined(STM32_SPI_SPI4_TX_DMA_STREAM))
|
|
#error "SPI4 DMA streams not defined"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_STREAM) || \
|
|
!defined(STM32_SPI_SPI5_TX_DMA_STREAM))
|
|
#error "SPI5 DMA streams not defined"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_DMA_STREAM) || \
|
|
!defined(STM32_SPI_SPI6_TX_DMA_STREAM))
|
|
#error "SPI6 DMA streams not defined"
|
|
#endif
|
|
|
|
/* Check on the validity of the assigned DMA channels.*/
|
|
#if STM32_SPI_USE_SPI1 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
|
|
#error "invalid DMA stream associated to SPI1 RX"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI1 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
|
|
#error "invalid DMA stream associated to SPI1 TX"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI2 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
|
|
#error "invalid DMA stream associated to SPI2 RX"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI2 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
|
|
#error "invalid DMA stream associated to SPI2 TX"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI3 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
|
|
#error "invalid DMA stream associated to SPI3 RX"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI3 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
|
|
#error "invalid DMA stream associated to SPI3 TX"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI4 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_RX_DMA_STREAM, STM32_SPI4_RX_DMA_MSK)
|
|
#error "invalid DMA stream associated to SPI4 RX"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI4 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_TX_DMA_STREAM, STM32_SPI4_TX_DMA_MSK)
|
|
#error "invalid DMA stream associated to SPI4 TX"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI5 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_RX_DMA_STREAM, STM32_SPI5_RX_DMA_MSK)
|
|
#error "invalid DMA stream associated to SPI5 RX"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI5 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_TX_DMA_STREAM, STM32_SPI5_TX_DMA_MSK)
|
|
#error "invalid DMA stream associated to SPI5 TX"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI6 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_RX_DMA_STREAM, STM32_SPI6_RX_DMA_MSK)
|
|
#error "invalid DMA stream associated to SPI6 RX"
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI6 && \
|
|
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_TX_DMA_STREAM, STM32_SPI6_TX_DMA_MSK)
|
|
#error "invalid DMA stream associated to SPI6 TX"
|
|
#endif
|
|
#endif /* STM32_ADVANCED_DMA */
|
|
|
|
#if !defined(STM32_DMA_REQUIRED)
|
|
#define STM32_DMA_REQUIRED
|
|
#endif
|
|
|
|
/*===========================================================================*/
|
|
/* Driver data structures and types. */
|
|
/*===========================================================================*/
|
|
|
|
/**
|
|
* @brief Type of a structure representing an SPI driver.
|
|
*/
|
|
typedef struct SPIDriver SPIDriver;
|
|
|
|
/**
|
|
* @brief SPI notification callback type.
|
|
*
|
|
* @param[in] spip pointer to the @p SPIDriver object triggering the
|
|
* callback
|
|
*/
|
|
typedef void (*spicallback_t)(SPIDriver *spip);
|
|
|
|
/**
|
|
* @brief Driver configuration structure.
|
|
*/
|
|
typedef struct {
|
|
/**
|
|
* @brief Operation complete callback or @p NULL.
|
|
*/
|
|
spicallback_t end_cb;
|
|
/* End of the mandatory fields.*/
|
|
/**
|
|
* @brief The chip select line port.
|
|
*/
|
|
ioportid_t ssport;
|
|
/**
|
|
* @brief The chip select line pad number.
|
|
*/
|
|
uint16_t sspad;
|
|
/**
|
|
* @brief SPI CR1 register initialization data.
|
|
*/
|
|
uint16_t cr1;
|
|
/**
|
|
* @brief SPI CR2 register initialization data.
|
|
*/
|
|
uint16_t cr2;
|
|
} SPIConfig;
|
|
|
|
/**
|
|
* @brief Structure representing an SPI driver.
|
|
*/
|
|
struct SPIDriver {
|
|
/**
|
|
* @brief Driver state.
|
|
*/
|
|
spistate_t state;
|
|
/**
|
|
* @brief Current configuration data.
|
|
*/
|
|
const SPIConfig *config;
|
|
#if SPI_USE_WAIT || defined(__DOXYGEN__)
|
|
/**
|
|
* @brief Waiting thread.
|
|
*/
|
|
thread_reference_t thread;
|
|
#endif /* SPI_USE_WAIT */
|
|
#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
|
/**
|
|
* @brief Mutex protecting the peripheral.
|
|
*/
|
|
mutex_t mutex;
|
|
#endif /* SPI_USE_MUTUAL_EXCLUSION */
|
|
#if defined(SPI_DRIVER_EXT_FIELDS)
|
|
SPI_DRIVER_EXT_FIELDS
|
|
#endif
|
|
/* End of the mandatory fields.*/
|
|
/**
|
|
* @brief Pointer to the SPIx registers block.
|
|
*/
|
|
SPI_TypeDef *spi;
|
|
/**
|
|
* @brief Receive DMA stream.
|
|
*/
|
|
const stm32_dma_stream_t *dmarx;
|
|
/**
|
|
* @brief Transmit DMA stream.
|
|
*/
|
|
const stm32_dma_stream_t *dmatx;
|
|
/**
|
|
* @brief RX DMA mode bit mask.
|
|
*/
|
|
uint32_t rxdmamode;
|
|
/**
|
|
* @brief TX DMA mode bit mask.
|
|
*/
|
|
uint32_t txdmamode;
|
|
};
|
|
|
|
/*===========================================================================*/
|
|
/* Driver macros. */
|
|
/*===========================================================================*/
|
|
|
|
/*===========================================================================*/
|
|
/* External declarations. */
|
|
/*===========================================================================*/
|
|
|
|
#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
|
|
extern SPIDriver SPID1;
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
|
|
extern SPIDriver SPID2;
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__)
|
|
extern SPIDriver SPID3;
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI4 && !defined(__DOXYGEN__)
|
|
extern SPIDriver SPID4;
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI5 && !defined(__DOXYGEN__)
|
|
extern SPIDriver SPID5;
|
|
#endif
|
|
|
|
#if STM32_SPI_USE_SPI6 && !defined(__DOXYGEN__)
|
|
extern SPIDriver SPID6;
|
|
#endif
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
void spi_lld_init(void);
|
|
void spi_lld_start(SPIDriver *spip);
|
|
void spi_lld_stop(SPIDriver *spip);
|
|
void spi_lld_select(SPIDriver *spip);
|
|
void spi_lld_unselect(SPIDriver *spip);
|
|
void spi_lld_ignore(SPIDriver *spip, size_t n);
|
|
void spi_lld_exchange(SPIDriver *spip, size_t n,
|
|
const void *txbuf, void *rxbuf);
|
|
void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
|
|
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
|
|
uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* HAL_USE_SPI */
|
|
|
|
#endif /* HAL_SPI_LLD_H */
|
|
|
|
/** @} */
|