662 lines
23 KiB
C
Executable File
662 lines
23 KiB
C
Executable File
/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPIv2/hal_spi_lld.c
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* @brief STM32 SPI subsystem low level driver source.
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*
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* @addtogroup SPI
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_SPI || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define SPI1_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \
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STM32_SPI1_RX_DMA_CHN)
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#define SPI1_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \
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STM32_SPI1_TX_DMA_CHN)
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#define SPI2_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \
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STM32_SPI2_RX_DMA_CHN)
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#define SPI2_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \
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STM32_SPI2_TX_DMA_CHN)
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#define SPI3_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \
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STM32_SPI3_RX_DMA_CHN)
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#define SPI3_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \
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STM32_SPI3_TX_DMA_CHN)
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#define SPI4_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_RX_DMA_STREAM, \
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STM32_SPI4_RX_DMA_CHN)
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#define SPI4_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_TX_DMA_STREAM, \
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STM32_SPI4_TX_DMA_CHN)
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#define SPI5_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_RX_DMA_STREAM, \
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STM32_SPI5_RX_DMA_CHN)
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#define SPI5_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_TX_DMA_STREAM, \
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STM32_SPI5_TX_DMA_CHN)
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#define SPI6_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_RX_DMA_STREAM, \
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STM32_SPI6_RX_DMA_CHN)
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#define SPI6_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_TX_DMA_STREAM, \
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STM32_SPI6_TX_DMA_CHN)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief SPI1 driver identifier.*/
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#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)
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SPIDriver SPID1;
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#endif
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/** @brief SPI2 driver identifier.*/
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#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__)
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SPIDriver SPID2;
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#endif
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/** @brief SPI3 driver identifier.*/
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#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__)
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SPIDriver SPID3;
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#endif
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/** @brief SPI4 driver identifier.*/
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#if STM32_SPI_USE_SPI4 || defined(__DOXYGEN__)
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SPIDriver SPID4;
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#endif
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/** @brief SPI5 driver identifier.*/
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#if STM32_SPI_USE_SPI5 || defined(__DOXYGEN__)
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SPIDriver SPID5;
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#endif
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/** @brief SPI6 driver identifier.*/
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#if STM32_SPI_USE_SPI6 || defined(__DOXYGEN__)
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SPIDriver SPID6;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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static const uint16_t dummytx = 0xFFFFU;
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static uint16_t dummyrx;
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Shared end-of-rx service routine.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
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/* DMA errors handling.*/
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#if defined(STM32_SPI_DMA_ERROR_HOOK)
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_SPI_DMA_ERROR_HOOK(spip);
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}
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#else
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(void)flags;
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#endif
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/* Stop everything.*/
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dmaStreamDisable(spip->dmatx);
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dmaStreamDisable(spip->dmarx);
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/* Portable SPI ISR code defined in the high level driver, note, it is
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a macro.*/
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_spi_isr_code(spip);
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}
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/**
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* @brief Shared end-of-tx service routine.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
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/* DMA errors handling.*/
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#if defined(STM32_SPI_DMA_ERROR_HOOK)
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(void)spip;
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_SPI_DMA_ERROR_HOOK(spip);
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}
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#else
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(void)spip;
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(void)flags;
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#endif
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level SPI driver initialization.
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*
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* @notapi
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*/
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void spi_lld_init(void) {
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#if STM32_SPI_USE_SPI1
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spiObjectInit(&SPID1);
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SPID1.spi = SPI1;
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SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
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SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
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SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#endif
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#if STM32_SPI_USE_SPI2
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spiObjectInit(&SPID2);
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SPID2.spi = SPI2;
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SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
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SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
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SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#endif
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#if STM32_SPI_USE_SPI3
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spiObjectInit(&SPID3);
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SPID3.spi = SPI3;
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SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
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SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
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SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#endif
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#if STM32_SPI_USE_SPI4
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spiObjectInit(&SPID4);
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SPID4.spi = SPI4;
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SPID4.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM);
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SPID4.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM);
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SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#endif
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#if STM32_SPI_USE_SPI5
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spiObjectInit(&SPID5);
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SPID5.spi = SPI5;
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SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM);
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SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM);
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SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#endif
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#if STM32_SPI_USE_SPI6
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spiObjectInit(&SPID6);
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SPID6.spi = SPI6;
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SPID6.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM);
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SPID6.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM);
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SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#endif
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}
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/**
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* @brief Configures and activates the SPI peripheral.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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*
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* @notapi
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*/
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void spi_lld_start(SPIDriver *spip) {
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uint32_t ds;
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/* If in stopped state then enables the SPI and DMA clocks.*/
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if (spip->state == SPI_STOP) {
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#if STM32_SPI_USE_SPI1
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if (&SPID1 == spip) {
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bool b;
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b = dmaStreamAllocate(spip->dmarx,
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STM32_SPI_SPI1_IRQ_PRIORITY,
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(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
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(void *)spip);
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osalDbgAssert(!b, "stream already allocated");
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b = dmaStreamAllocate(spip->dmatx,
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STM32_SPI_SPI1_IRQ_PRIORITY,
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(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
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(void *)spip);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableSPI1(FALSE);
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}
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#endif
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#if STM32_SPI_USE_SPI2
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if (&SPID2 == spip) {
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bool b;
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b = dmaStreamAllocate(spip->dmarx,
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STM32_SPI_SPI2_IRQ_PRIORITY,
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(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
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(void *)spip);
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osalDbgAssert(!b, "stream already allocated");
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b = dmaStreamAllocate(spip->dmatx,
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STM32_SPI_SPI2_IRQ_PRIORITY,
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(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
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(void *)spip);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableSPI2(FALSE);
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}
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#endif
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#if STM32_SPI_USE_SPI3
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if (&SPID3 == spip) {
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bool b;
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b = dmaStreamAllocate(spip->dmarx,
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STM32_SPI_SPI3_IRQ_PRIORITY,
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(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
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(void *)spip);
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osalDbgAssert(!b, "stream already allocated");
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b = dmaStreamAllocate(spip->dmatx,
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STM32_SPI_SPI3_IRQ_PRIORITY,
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(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
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(void *)spip);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableSPI3(FALSE);
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}
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#endif
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#if STM32_SPI_USE_SPI4
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if (&SPID4 == spip) {
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bool b;
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b = dmaStreamAllocate(spip->dmarx,
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STM32_SPI_SPI4_IRQ_PRIORITY,
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(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
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(void *)spip);
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osalDbgAssert(!b, "stream already allocated");
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b = dmaStreamAllocate(spip->dmatx,
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STM32_SPI_SPI4_IRQ_PRIORITY,
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(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
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(void *)spip);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableSPI4(FALSE);
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}
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#endif
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#if STM32_SPI_USE_SPI5
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if (&SPID5 == spip) {
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bool b;
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b = dmaStreamAllocate(spip->dmarx,
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STM32_SPI_SPI5_IRQ_PRIORITY,
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(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
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(void *)spip);
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osalDbgAssert(!b, "stream already allocated");
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b = dmaStreamAllocate(spip->dmatx,
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STM32_SPI_SPI5_IRQ_PRIORITY,
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(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
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(void *)spip);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableSPI5(FALSE);
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}
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#endif
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#if STM32_SPI_USE_SPI6
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if (&SPID6 == spip) {
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bool b;
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b = dmaStreamAllocate(spip->dmarx,
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STM32_SPI_SPI6_IRQ_PRIORITY,
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(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
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(void *)spip);
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osalDbgAssert(!b, "stream already allocated");
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b = dmaStreamAllocate(spip->dmatx,
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STM32_SPI_SPI6_IRQ_PRIORITY,
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(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
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(void *)spip);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableSPI6(FALSE);
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}
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#endif
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/* DMA setup.*/
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dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR);
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dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR);
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}
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/* Configuration-specific DMA setup.*/
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ds = spip->config->cr2 & SPI_CR2_DS;
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if (!ds || (ds <= (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0))) {
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/* Frame width is 8 bits or smaller.*/
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spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
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STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
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spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
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STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
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}
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else {
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/* Frame width is larger than 8 bits.*/
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spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
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STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
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spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
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STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
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}
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/* SPI setup and enable.*/
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spip->spi->CR1 &= ~SPI_CR1_SPE;
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spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR;
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spip->spi->CR2 = spip->config->cr2 | SPI_CR2_FRXTH | SPI_CR2_SSOE |
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SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
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spip->spi->CR1 |= SPI_CR1_SPE;
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}
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/**
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* @brief Deactivates the SPI peripheral.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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|
*
|
|
* @notapi
|
|
*/
|
|
void spi_lld_stop(SPIDriver *spip) {
|
|
|
|
/* If in ready state then disables the SPI clock.*/
|
|
if (spip->state == SPI_READY) {
|
|
|
|
/* SPI disable.*/
|
|
spip->spi->CR1 &= ~SPI_CR1_SPE;
|
|
spip->spi->CR1 = 0;
|
|
spip->spi->CR2 = 0;
|
|
dmaStreamRelease(spip->dmarx);
|
|
dmaStreamRelease(spip->dmatx);
|
|
|
|
#if STM32_SPI_USE_SPI1
|
|
if (&SPID1 == spip)
|
|
rccDisableSPI1(FALSE);
|
|
#endif
|
|
#if STM32_SPI_USE_SPI2
|
|
if (&SPID2 == spip)
|
|
rccDisableSPI2(FALSE);
|
|
#endif
|
|
#if STM32_SPI_USE_SPI3
|
|
if (&SPID3 == spip)
|
|
rccDisableSPI3(FALSE);
|
|
#endif
|
|
#if STM32_SPI_USE_SPI4
|
|
if (&SPID4 == spip)
|
|
rccDisableSPI4(FALSE);
|
|
#endif
|
|
#if STM32_SPI_USE_SPI5
|
|
if (&SPID5 == spip)
|
|
rccDisableSPI5(FALSE);
|
|
#endif
|
|
#if STM32_SPI_USE_SPI6
|
|
if (&SPID6 == spip)
|
|
rccDisableSPI6(FALSE);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Asserts the slave select signal and prepares for transfers.
|
|
*
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void spi_lld_select(SPIDriver *spip) {
|
|
|
|
palClearPad(spip->config->ssport, spip->config->sspad);
|
|
}
|
|
|
|
/**
|
|
* @brief Deasserts the slave select signal.
|
|
* @details The previously selected peripheral is unselected.
|
|
*
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void spi_lld_unselect(SPIDriver *spip) {
|
|
|
|
palSetPad(spip->config->ssport, spip->config->sspad);
|
|
}
|
|
|
|
/**
|
|
* @brief Ignores data on the SPI bus.
|
|
* @details This asynchronous function starts the transmission of a series of
|
|
* idle words on the SPI bus and ignores the received data.
|
|
* @post At the end of the operation the configured callback is invoked.
|
|
*
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
* @param[in] n number of words to be ignored
|
|
*
|
|
* @notapi
|
|
*/
|
|
void spi_lld_ignore(SPIDriver *spip, size_t n) {
|
|
|
|
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
|
|
|
|
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
|
|
dmaStreamSetTransactionSize(spip->dmarx, n);
|
|
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
|
|
|
|
dmaStreamSetMemory0(spip->dmatx, &dummytx);
|
|
dmaStreamSetTransactionSize(spip->dmatx, n);
|
|
dmaStreamSetMode(spip->dmatx, spip->txdmamode);
|
|
|
|
dmaStreamEnable(spip->dmarx);
|
|
dmaStreamEnable(spip->dmatx);
|
|
}
|
|
|
|
/**
|
|
* @brief Exchanges data on the SPI bus.
|
|
* @details This asynchronous function starts a simultaneous transmit/receive
|
|
* operation.
|
|
* @post At the end of the operation the configured callback is invoked.
|
|
* @note The buffers are organized as uint8_t arrays for data sizes below or
|
|
* equal to 8 bits else it is organized as uint16_t arrays.
|
|
*
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
* @param[in] n number of words to be exchanged
|
|
* @param[in] txbuf the pointer to the transmit buffer
|
|
* @param[out] rxbuf the pointer to the receive buffer
|
|
*
|
|
* @notapi
|
|
*/
|
|
void spi_lld_exchange(SPIDriver *spip, size_t n,
|
|
const void *txbuf, void *rxbuf) {
|
|
|
|
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
|
|
|
|
dmaStreamSetMemory0(spip->dmarx, rxbuf);
|
|
dmaStreamSetTransactionSize(spip->dmarx, n);
|
|
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
|
|
|
|
dmaStreamSetMemory0(spip->dmatx, txbuf);
|
|
dmaStreamSetTransactionSize(spip->dmatx, n);
|
|
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
|
|
|
|
dmaStreamEnable(spip->dmarx);
|
|
dmaStreamEnable(spip->dmatx);
|
|
}
|
|
|
|
/**
|
|
* @brief Sends data over the SPI bus.
|
|
* @details This asynchronous function starts a transmit operation.
|
|
* @post At the end of the operation the configured callback is invoked.
|
|
* @note The buffers are organized as uint8_t arrays for data sizes below or
|
|
* equal to 8 bits else it is organized as uint16_t arrays.
|
|
*
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
* @param[in] n number of words to send
|
|
* @param[in] txbuf the pointer to the transmit buffer
|
|
*
|
|
* @notapi
|
|
*/
|
|
void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
|
|
|
|
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
|
|
|
|
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
|
|
dmaStreamSetTransactionSize(spip->dmarx, n);
|
|
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
|
|
|
|
dmaStreamSetMemory0(spip->dmatx, txbuf);
|
|
dmaStreamSetTransactionSize(spip->dmatx, n);
|
|
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
|
|
|
|
dmaStreamEnable(spip->dmarx);
|
|
dmaStreamEnable(spip->dmatx);
|
|
}
|
|
|
|
/**
|
|
* @brief Receives data from the SPI bus.
|
|
* @details This asynchronous function starts a receive operation.
|
|
* @post At the end of the operation the configured callback is invoked.
|
|
* @note The buffers are organized as uint8_t arrays for data sizes below or
|
|
* equal to 8 bits else it is organized as uint16_t arrays.
|
|
*
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
* @param[in] n number of words to receive
|
|
* @param[out] rxbuf the pointer to the receive buffer
|
|
*
|
|
* @notapi
|
|
*/
|
|
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
|
|
|
|
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
|
|
|
|
dmaStreamSetMemory0(spip->dmarx, rxbuf);
|
|
dmaStreamSetTransactionSize(spip->dmarx, n);
|
|
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
|
|
|
|
dmaStreamSetMemory0(spip->dmatx, &dummytx);
|
|
dmaStreamSetTransactionSize(spip->dmatx, n);
|
|
dmaStreamSetMode(spip->dmatx, spip->txdmamode);
|
|
|
|
dmaStreamEnable(spip->dmarx);
|
|
dmaStreamEnable(spip->dmatx);
|
|
}
|
|
|
|
/**
|
|
* @brief Exchanges one frame using a polled wait.
|
|
* @details This synchronous function exchanges one frame using a polled
|
|
* synchronization method. This function is useful when exchanging
|
|
* small amount of data on high speed channels, usually in this
|
|
* situation is much more efficient just wait for completion using
|
|
* polling than suspending the thread waiting for an interrupt.
|
|
*
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
* @param[in] frame the data frame to send over the SPI bus
|
|
* @return The received data frame from the SPI bus.
|
|
*/
|
|
uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
|
|
|
|
/*
|
|
* Data register must be accessed with the appropriate data size.
|
|
* Byte size access (uint8_t *) for transactions that are <= 8-bit.
|
|
* Halfword size access (uint16_t) for transactions that are <= 8-bit.
|
|
*/
|
|
if ((spip->config->cr2 & SPI_CR2_DS) <= (SPI_CR2_DS_2 |
|
|
SPI_CR2_DS_1 |
|
|
SPI_CR2_DS_0)) {
|
|
volatile uint8_t *spidr = (volatile uint8_t *)&spip->spi->DR;
|
|
*spidr = (uint8_t)frame;
|
|
while ((spip->spi->SR & SPI_SR_RXNE) == 0)
|
|
;
|
|
return (uint16_t)*spidr;
|
|
}
|
|
else {
|
|
spip->spi->DR = frame;
|
|
while ((spip->spi->SR & SPI_SR_RXNE) == 0)
|
|
;
|
|
return spip->spi->DR;
|
|
}
|
|
}
|
|
|
|
#endif /* HAL_USE_SPI */
|
|
|
|
/** @} */
|