578 lines
19 KiB
C
Executable File
578 lines
19 KiB
C
Executable File
/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPIv2/hal_i2s_lld.c
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* @brief STM32 I2S subsystem low level driver source.
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*
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* @addtogroup I2S
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_I2S || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define I2S1_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_RX_DMA_STREAM, \
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STM32_SPI1_RX_DMA_CHN)
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#define I2S1_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_TX_DMA_STREAM, \
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STM32_SPI1_TX_DMA_CHN)
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#define I2S2_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_RX_DMA_STREAM, \
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STM32_SPI2_RX_DMA_CHN)
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#define I2S2_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_TX_DMA_STREAM, \
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STM32_SPI2_TX_DMA_CHN)
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#define I2S3_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_RX_DMA_STREAM, \
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STM32_SPI3_RX_DMA_CHN)
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#define I2S3_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_TX_DMA_STREAM, \
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STM32_SPI3_TX_DMA_CHN)
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/*
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* Static I2S settings for I2S1.
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*/
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#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE)
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#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
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#define STM32_I2S1_CFGR_CFG 0
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#endif
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
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#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
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#endif
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#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */
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#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
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#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
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#endif
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
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#define STM32_I2S1_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
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SPI_I2SCFGR_I2SCFG_0)
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#endif
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#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */
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/*
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* Static I2S settings for I2S2.
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*/
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#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE)
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#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
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#define STM32_I2S2_CFGR_CFG 0
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#endif
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
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#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
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#endif
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#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
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#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
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#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
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#endif
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
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#define STM32_I2S2_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
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SPI_I2SCFGR_I2SCFG_0)
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#endif
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#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
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/*
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* Static I2S settings for I2S3.
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*/
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#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE)
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#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
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#define STM32_I2S3_CFGR_CFG 0
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#endif
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
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#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
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#endif
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#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
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#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
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#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
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#endif
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
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#define STM32_I2S3_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
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SPI_I2SCFGR_I2SCFG_0)
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#endif
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#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief I2S1 driver identifier.*/
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#if STM32_I2S_USE_SPI1 || defined(__DOXYGEN__)
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I2SDriver I2SD1;
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#endif
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/** @brief I2S2 driver identifier.*/
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#if STM32_I2S_USE_SPI2 || defined(__DOXYGEN__)
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I2SDriver I2SD2;
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#endif
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/** @brief I2S3 driver identifier.*/
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#if STM32_I2S_USE_SPI3 || defined(__DOXYGEN__)
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I2SDriver I2SD3;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) || \
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STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) || \
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STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
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/**
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* @brief Shared end-of-rx service routine.
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*
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* @param[in] i2sp pointer to the @p I2SDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) {
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(void)i2sp;
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/* DMA errors handling.*/
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#if defined(STM32_I2S_DMA_ERROR_HOOK)
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_I2S_DMA_ERROR_HOOK(i2sp);
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}
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#endif
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/* Callbacks handling, note it is portable code defined in the high
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level driver.*/
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if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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/* Transfer complete processing.*/
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_i2s_isr_full_code(i2sp);
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}
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else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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/* Half transfer processing.*/
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_i2s_isr_half_code(i2sp);
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}
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}
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#endif
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#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) || \
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STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) || \
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STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
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/**
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* @brief Shared end-of-tx service routine.
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*
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* @param[in] i2sp pointer to the @p I2SDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) {
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(void)i2sp;
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/* DMA errors handling.*/
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#if defined(STM32_I2S_DMA_ERROR_HOOK)
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_I2S_DMA_ERROR_HOOK(i2sp);
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}
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#endif
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/* Callbacks handling, note it is portable code defined in the high
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level driver.*/
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if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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/* Transfer complete processing.*/
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_i2s_isr_full_code(i2sp);
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}
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else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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/* Half transfer processing.*/
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_i2s_isr_half_code(i2sp);
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}
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}
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#endif
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level I2S driver initialization.
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*
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* @notapi
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*/
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void i2s_lld_init(void) {
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#if STM32_I2S_USE_SPI1
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i2sObjectInit(&I2SD1);
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I2SD1.spi = SPI1;
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I2SD1.cfg = STM32_I2S1_CFGR_CFG;
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
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I2SD1.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI1_RX_DMA_STREAM);
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I2SD1.rxdmamode = STM32_DMA_CR_CHSEL(I2S1_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
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STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MSIZE_HWORD |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#else
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I2SD1.dmarx = NULL;
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I2SD1.rxdmamode = 0;
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#endif
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#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
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I2SD1.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI1_TX_DMA_STREAM);
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I2SD1.txdmamode = STM32_DMA_CR_CHSEL(I2S1_TX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
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STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MSIZE_HWORD |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#else
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I2SD1.dmatx = NULL;
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I2SD1.txdmamode = 0;
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#endif
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#endif
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#if STM32_I2S_USE_SPI2
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i2sObjectInit(&I2SD2);
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I2SD2.spi = SPI2;
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I2SD2.cfg = STM32_I2S2_CFGR_CFG;
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
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I2SD2.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI2_RX_DMA_STREAM);
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I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
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STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MSIZE_HWORD |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#else
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I2SD2.dmarx = NULL;
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I2SD2.rxdmamode = 0;
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#endif
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#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
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I2SD2.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI2_TX_DMA_STREAM);
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I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
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STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MSIZE_HWORD |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#else
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I2SD2.dmatx = NULL;
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I2SD2.txdmamode = 0;
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#endif
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#endif
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#if STM32_I2S_USE_SPI3
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i2sObjectInit(&I2SD3);
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I2SD3.spi = SPI3;
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I2SD3.cfg = STM32_I2S3_CFGR_CFG;
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
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I2SD3.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI3_RX_DMA_STREAM);
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I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
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STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MSIZE_HWORD |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#else
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I2SD3.dmarx = NULL;
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I2SD3.rxdmamode = 0;
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#endif
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#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
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I2SD3.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI3_TX_DMA_STREAM);
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I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
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STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MSIZE_HWORD |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#else
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I2SD3.dmatx = NULL;
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I2SD3.txdmamode = 0;
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#endif
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#endif
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}
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/**
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* @brief Configures and activates the I2S peripheral.
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*
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* @param[in] i2sp pointer to the @p I2SDriver object
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*
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* @notapi
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*/
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void i2s_lld_start(I2SDriver *i2sp) {
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/* If in stopped state then enables the SPI and DMA clocks.*/
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if (i2sp->state == I2S_STOP) {
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#if STM32_I2S_USE_SPI1
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if (&I2SD1 == i2sp) {
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bool b;
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/* Enabling I2S unit clock.*/
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rccEnableSPI1(FALSE);
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
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b = dmaStreamAllocate(i2sp->dmarx,
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STM32_I2S_SPI1_IRQ_PRIORITY,
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(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
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(void *)i2sp);
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osalDbgAssert(!b, "stream already allocated");
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/* CRs settings are done here because those never changes until
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the driver is stopped.*/
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i2sp->spi->CR1 = 0;
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i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
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#endif
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#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
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b = dmaStreamAllocate(i2sp->dmatx,
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STM32_I2S_SPI1_IRQ_PRIORITY,
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(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
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(void *)i2sp);
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osalDbgAssert(!b, "stream already allocated");
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/* CRs settings are done here because those never changes until
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the driver is stopped.*/
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i2sp->spi->CR1 = 0;
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i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
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#endif
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}
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#endif
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#if STM32_I2S_USE_SPI2
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if (&I2SD2 == i2sp) {
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bool b;
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/* Enabling I2S unit clock.*/
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rccEnableSPI2(FALSE);
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#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
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b = dmaStreamAllocate(i2sp->dmarx,
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STM32_I2S_SPI2_IRQ_PRIORITY,
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(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
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(void *)i2sp);
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osalDbgAssert(!b, "stream already allocated");
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/* CRs settings are done here because those never changes until
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the driver is stopped.*/
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i2sp->spi->CR1 = 0;
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i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
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#endif
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#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
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b = dmaStreamAllocate(i2sp->dmatx,
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STM32_I2S_SPI2_IRQ_PRIORITY,
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(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
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(void *)i2sp);
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osalDbgAssert(!b, "stream already allocated");
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/* CRs settings are done here because those never changes until
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the driver is stopped.*/
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i2sp->spi->CR1 = 0;
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i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if STM32_I2S_USE_SPI3
|
|
if (&I2SD3 == i2sp) {
|
|
bool b;
|
|
|
|
/* Enabling I2S unit clock.*/
|
|
rccEnableSPI3(FALSE);
|
|
|
|
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
|
|
b = dmaStreamAllocate(i2sp->dmarx,
|
|
STM32_I2S_SPI3_IRQ_PRIORITY,
|
|
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
|
|
(void *)i2sp);
|
|
osalDbgAssert(!b, "stream already allocated");
|
|
|
|
/* CRs settings are done here because those never changes until
|
|
the driver is stopped.*/
|
|
i2sp->spi->CR1 = 0;
|
|
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
|
|
#endif
|
|
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
|
|
b = dmaStreamAllocate(i2sp->dmatx,
|
|
STM32_I2S_SPI3_IRQ_PRIORITY,
|
|
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
|
|
(void *)i2sp);
|
|
osalDbgAssert(!b, "stream already allocated");
|
|
|
|
/* CRs settings are done here because those never changes until
|
|
the driver is stopped.*/
|
|
i2sp->spi->CR1 = 0;
|
|
i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
|
|
#endif
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* I2S (re)configuration.*/
|
|
i2sp->spi->I2SPR = i2sp->config->i2spr;
|
|
i2sp->spi->I2SCFGR = i2sp->config->i2scfgr | i2sp->cfg | SPI_I2SCFGR_I2SMOD;
|
|
}
|
|
|
|
/**
|
|
* @brief Deactivates the I2S peripheral.
|
|
*
|
|
* @param[in] i2sp pointer to the @p I2SDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void i2s_lld_stop(I2SDriver *i2sp) {
|
|
|
|
/* If in ready state then disables the SPI clock.*/
|
|
if (i2sp->state == I2S_READY) {
|
|
|
|
/* SPI disable.*/
|
|
i2sp->spi->CR2 = 0;
|
|
if (NULL != i2sp->dmarx)
|
|
dmaStreamRelease(i2sp->dmarx);
|
|
if (NULL != i2sp->dmatx)
|
|
dmaStreamRelease(i2sp->dmatx);
|
|
|
|
#if STM32_I2S_USE_SPI1
|
|
if (&I2SD1 == i2sp)
|
|
rccDisableSPI1(FALSE);
|
|
#endif
|
|
|
|
#if STM32_I2S_USE_SPI2
|
|
if (&I2SD2 == i2sp)
|
|
rccDisableSPI2(FALSE);
|
|
#endif
|
|
|
|
#if STM32_I2S_USE_SPI3
|
|
if (&I2SD3 == i2sp)
|
|
rccDisableSPI3(FALSE);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Starts a I2S data exchange.
|
|
*
|
|
* @param[in] i2sp pointer to the @p I2SDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void i2s_lld_start_exchange(I2SDriver *i2sp) {
|
|
size_t size = i2sp->config->size;
|
|
|
|
/* In 32 bit modes the DMA has to perform double operations because fetches
|
|
are always performed using 16 bit accesses.
|
|
DATLEN CHLEN SIZE
|
|
00 (16) 0 (16) 16
|
|
00 (16) 1 (32) 16
|
|
01 (24) X 32
|
|
10 (32) X 32
|
|
11 (NA) X NA
|
|
*/
|
|
if ((i2sp->config->i2scfgr & SPI_I2SCFGR_DATLEN) != 0)
|
|
size *= 2;
|
|
|
|
/* RX DMA setup.*/
|
|
if (NULL != i2sp->dmarx) {
|
|
dmaStreamSetMode(i2sp->dmarx, i2sp->rxdmamode);
|
|
dmaStreamSetPeripheral(i2sp->dmarx, &i2sp->spi->DR);
|
|
dmaStreamSetMemory0(i2sp->dmarx, i2sp->config->rx_buffer);
|
|
dmaStreamSetTransactionSize(i2sp->dmarx, size);
|
|
dmaStreamEnable(i2sp->dmarx);
|
|
}
|
|
|
|
/* TX DMA setup.*/
|
|
if (NULL != i2sp->dmatx) {
|
|
dmaStreamSetMode(i2sp->dmatx, i2sp->txdmamode);
|
|
dmaStreamSetPeripheral(i2sp->dmatx, &i2sp->spi->DR);
|
|
dmaStreamSetMemory0(i2sp->dmatx, i2sp->config->tx_buffer);
|
|
dmaStreamSetTransactionSize(i2sp->dmatx, size);
|
|
dmaStreamEnable(i2sp->dmatx);
|
|
}
|
|
|
|
/* Starting transfer.*/
|
|
i2sp->spi->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
|
}
|
|
|
|
/**
|
|
* @brief Stops the ongoing data exchange.
|
|
* @details The ongoing data exchange, if any, is stopped, if the driver
|
|
* was not active the function does nothing.
|
|
*
|
|
* @param[in] i2sp pointer to the @p I2SDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void i2s_lld_stop_exchange(I2SDriver *i2sp) {
|
|
|
|
/* Stop TX DMA, if enabled.*/
|
|
if (NULL != i2sp->dmatx) {
|
|
dmaStreamDisable(i2sp->dmatx);
|
|
|
|
/* From the RM: To switch off the I2S, by clearing I2SE, it is mandatory
|
|
to wait for TXE = 1 and BSY = 0.*/
|
|
while ((i2sp->spi->SR & (SPI_SR_TXE | SPI_SR_BSY)) != SPI_SR_TXE)
|
|
;
|
|
}
|
|
|
|
/* Stop SPI/I2S peripheral.*/
|
|
i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
|
|
|
|
/* Stop RX DMA, if enabled.*/
|
|
if (NULL != i2sp->dmarx)
|
|
dmaStreamDisable(i2sp->dmarx);
|
|
}
|
|
|
|
#endif /* HAL_USE_I2S */
|
|
|
|
/** @} */
|