514 lines
16 KiB
C
Executable File
514 lines
16 KiB
C
Executable File
/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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Concepts and parts of this file have been contributed by Uladzimir Pylinsky
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aka barthess.
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*/
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/**
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* @file I2Cv1/hal_i2c_lld.h
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* @brief STM32 I2C subsystem low level driver header.
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*
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* @addtogroup I2C
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* @{
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*/
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#ifndef HAL_I2C_LLD_H
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#define HAL_I2C_LLD_H
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#if HAL_USE_I2C || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Peripheral clock frequency.
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*/
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#define I2C_CLK_FREQ ((STM32_PCLK1) / 1000000)
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief I2C1 driver enable switch.
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* @details If set to @p TRUE the support for I2C1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
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#define STM32_I2C_USE_I2C1 FALSE
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#endif
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/**
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* @brief I2C2 driver enable switch.
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* @details If set to @p TRUE the support for I2C2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
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#define STM32_I2C_USE_I2C2 FALSE
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#endif
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/**
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* @brief I2C3 driver enable switch.
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* @details If set to @p TRUE the support for I2C3 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__)
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#define STM32_I2C_USE_I2C3 FALSE
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#endif
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/**
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* @brief I2C timeout on busy condition in milliseconds.
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*/
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#if !defined(STM32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__)
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#define STM32_I2C_BUSY_TIMEOUT 50
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#endif
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/**
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* @brief I2C1 interrupt priority level setting.
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*/
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#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief I2C2 interrupt priority level setting.
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*/
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#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C2_IRQ_PRIORITY 10
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#endif
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/**
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* @brief I2C3 interrupt priority level setting.
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*/
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#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C3_IRQ_PRIORITY 10
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#endif
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/**
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* @brief I2C1 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C1_DMA_PRIORITY 1
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#endif
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/**
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* @brief I2C2 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C2_DMA_PRIORITY 1
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#endif
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/**
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* @brief I2C3 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_I2C_I2C3_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C3_DMA_PRIORITY 1
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#endif
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/**
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* @brief I2C DMA error hook.
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* @note The default action for DMA errors is a system halt because DMA
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* error can only happen because programming errors.
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*/
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#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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#endif
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#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
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/**
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* @brief DMA stream used for I2C1 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#endif
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/**
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* @brief DMA stream used for I2C1 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#endif
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/**
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* @brief DMA stream used for I2C2 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#endif
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/**
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* @brief DMA stream used for I2C2 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#endif
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/**
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* @brief DMA stream used for I2C3 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#endif
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/**
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* @brief DMA stream used for I2C3 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#endif
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#else /* !STM32_ADVANCED_DMA */
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/* Fixed streams for platforms using the old DMA peripheral, the values are
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valid for both STM32F1xx and STM32L1xx.*/
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#endif /* !STM32_ADVANCED_DMA*/
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/* Flag for the whole STM32F1XX family. */
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#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
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defined(STM32F10X_HD_VL) || defined(STM32F10X_LD) || \
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defined(STM32F10X_MD) || defined(STM32F10X_HD) || \
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defined(STM32F10X_XL) || defined(STM32F10X_CL)
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#define STM32F1XX_I2C
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/** @brief error checks */
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#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
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#error "I2C1 not present in the selected device"
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#endif
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#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2
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#error "I2C2 not present in the selected device"
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#endif
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#if STM32_I2C_USE_I2C3 && !STM32_HAS_I2C3
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#error "I2C3 not present in the selected device"
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#endif
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#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 && \
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!STM32_I2C_USE_I2C3
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#error "I2C driver activated but no I2C peripheral assigned"
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#endif
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#if STM32_I2C_USE_I2C1 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C1_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to I2C1"
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#endif
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#if STM32_I2C_USE_I2C2 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C2_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to I2C2"
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#endif
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#if STM32_I2C_USE_I2C3 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C3_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to I2C3"
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#endif
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#if STM32_I2C_USE_I2C1 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C1_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to I2C1"
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#endif
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#if STM32_I2C_USE_I2C2 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C2_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to I2C2"
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#endif
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#if STM32_I2C_USE_I2C3 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C3_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to I2C3"
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#endif
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/* The following checks are only required when there is a DMA able to
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reassign streams to different channels.*/
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#if STM32_ADVANCED_DMA
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/* Check on the presence of the DMA streams settings in mcuconf.h.*/
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#if STM32_I2C_USE_I2C1 && (!defined(STM32_I2C_I2C1_RX_DMA_STREAM) || \
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!defined(STM32_I2C_I2C1_TX_DMA_STREAM))
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#error "I2C1 DMA streams not defined"
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#endif
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#if STM32_I2C_USE_I2C2 && (!defined(STM32_I2C_I2C2_RX_DMA_STREAM) || \
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!defined(STM32_I2C_I2C2_TX_DMA_STREAM))
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#error "I2C2 DMA streams not defined"
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#endif
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/* Check on the validity of the assigned DMA channels.*/
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#if STM32_I2C_USE_I2C1 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \
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STM32_I2C1_RX_DMA_MSK)
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#error "invalid DMA stream associated to I2C1 RX"
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#endif
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#if STM32_I2C_USE_I2C1 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \
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STM32_I2C1_TX_DMA_MSK)
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#error "invalid DMA stream associated to I2C1 TX"
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#endif
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#if STM32_I2C_USE_I2C2 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \
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STM32_I2C2_RX_DMA_MSK)
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#error "invalid DMA stream associated to I2C2 RX"
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#endif
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#if STM32_I2C_USE_I2C2 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \
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STM32_I2C2_TX_DMA_MSK)
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#error "invalid DMA stream associated to I2C2 TX"
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#endif
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#if STM32_I2C_USE_I2C3 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM, \
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STM32_I2C3_RX_DMA_MSK)
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#error "invalid DMA stream associated to I2C3 RX"
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#endif
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#if STM32_I2C_USE_I2C3 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM, \
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STM32_I2C3_TX_DMA_MSK)
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#error "invalid DMA stream associated to I2C3 TX"
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#endif
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#endif /* STM32_ADVANCED_DMA */
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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/* Check clock range. */
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#if defined(STM32F4XX)
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#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 42)
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#error "I2C peripheral clock frequency out of range."
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#endif
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#elif defined(STM32L1XX)
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#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 32)
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#error "I2C peripheral clock frequency out of range."
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#endif
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#elif defined(STM32F2XX)
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#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 30)
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#error "I2C peripheral clock frequency out of range."
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#endif
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#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
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defined(STM32F10X_HD_VL)
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#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 24)
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#error "I2C peripheral clock frequency out of range."
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#endif
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#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \
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defined(STM32F10X_HD) || defined(STM32F10X_XL) || \
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defined(STM32F10X_CL)
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#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 36)
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#error "I2C peripheral clock frequency out of range."
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#endif
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#else
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#error "unspecified, unsupported or invalid STM32 platform"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type representing an I2C address.
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*/
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typedef uint16_t i2caddr_t;
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/**
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* @brief Type of I2C driver condition flags.
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*/
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typedef uint32_t i2cflags_t;
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/**
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* @brief Supported modes for the I2C bus.
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*/
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typedef enum {
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OPMODE_I2C = 1,
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OPMODE_SMBUS_DEVICE = 2,
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OPMODE_SMBUS_HOST = 3,
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} i2copmode_t;
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/**
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* @brief Supported duty cycle modes for the I2C bus.
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*/
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typedef enum {
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STD_DUTY_CYCLE = 1,
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FAST_DUTY_CYCLE_2 = 2,
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FAST_DUTY_CYCLE_16_9 = 3,
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} i2cdutycycle_t;
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/**
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* @brief Type of I2C driver configuration structure.
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*/
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typedef struct {
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/* End of the mandatory fields.*/
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i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */
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uint32_t clock_speed; /**< @brief Specifies the clock frequency.
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@note Must be set to a value lower
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than 400kHz. */
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i2cdutycycle_t duty_cycle; /**< @brief Specifies the I2C fast mode
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duty cycle. */
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} I2CConfig;
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/**
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* @brief Type of a structure representing an I2C driver.
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*/
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typedef struct I2CDriver I2CDriver;
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/**
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* @brief Structure representing an I2C driver.
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*/
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struct I2CDriver {
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/**
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* @brief Driver state.
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*/
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i2cstate_t state;
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/**
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* @brief Current configuration data.
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*/
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const I2CConfig *config;
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/**
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* @brief Error flags.
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*/
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i2cflags_t errors;
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#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
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/**
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* @brief Mutex protecting the bus.
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*/
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mutex_t mutex;
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#endif /* I2C_USE_MUTUAL_EXCLUSION */
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#if defined(I2C_DRIVER_EXT_FIELDS)
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I2C_DRIVER_EXT_FIELDS
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief Thread waiting for I/O completion.
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*/
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thread_reference_t thread;
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/**
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* @brief Current slave address without R/W bit.
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*/
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i2caddr_t addr;
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/**
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* @brief RX DMA mode bit mask.
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*/
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uint32_t rxdmamode;
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/**
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* @brief TX DMA mode bit mask.
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*/
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uint32_t txdmamode;
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/**
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* @brief Receive DMA channel.
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*/
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const stm32_dma_stream_t *dmarx;
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/**
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* @brief Transmit DMA channel.
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*/
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const stm32_dma_stream_t *dmatx;
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/**
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* @brief Pointer to the I2Cx registers block.
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*/
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I2C_TypeDef *i2c;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Get errors from I2C driver.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if !defined(__DOXYGEN__)
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#if STM32_I2C_USE_I2C1
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extern I2CDriver I2CD1;
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#endif
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#if STM32_I2C_USE_I2C2
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extern I2CDriver I2CD2;
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#endif
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#if STM32_I2C_USE_I2C3
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extern I2CDriver I2CD3;
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#endif
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#endif /* !defined(__DOXYGEN__) */
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#ifdef __cplusplus
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extern "C" {
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#endif
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void i2c_lld_init(void);
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void i2c_lld_start(I2CDriver *i2cp);
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void i2c_lld_stop(I2CDriver *i2cp);
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msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
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const uint8_t *txbuf, size_t txbytes,
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uint8_t *rxbuf, size_t rxbytes,
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systime_t timeout);
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msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
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uint8_t *rxbuf, size_t rxbytes,
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|
systime_t timeout);
|
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#ifdef __cplusplus
|
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}
|
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#endif
|
|
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#endif /* HAL_USE_I2C */
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|
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#endif /* HAL_I2C_LLD_H */
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/** @} */
|