166 lines
4.9 KiB
ArmAsm
Executable File
166 lines
4.9 KiB
ArmAsm
Executable File
/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
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This file is part of ChibiOS.
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ChibiOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file compilers/GCC/chcoreasm_v7m.S
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* @brief ARMv7-M architecture port low level code.
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*
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* @addtogroup ARMCMx_GCC_CORE
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* @{
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*/
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#if !defined(FALSE) || defined(__DOXYGEN__)
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#define FALSE 0
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#endif
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#if !defined(TRUE) || defined(__DOXYGEN__)
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#define TRUE 1
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#endif
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#define _FROM_ASM_
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#include "chlicense.h"
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#include "chconf.h"
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#include "chcore.h"
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#if !defined(__DOXYGEN__)
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/*
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* RTOS-specific context offset.
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*/
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#if defined(_CHIBIOS_RT_CONF_)
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#define CONTEXT_OFFSET 12
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#elif defined(_CHIBIOS_NIL_CONF_)
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#define CONTEXT_OFFSET 0
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#else
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#error "invalid chconf.h"
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#endif
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.set SCB_ICSR, 0xE000ED04
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.set ICSR_PENDSVSET, 0x10000000
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.syntax unified
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.cpu cortex-m4
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#if CORTEX_USE_FPU
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.fpu fpv4-sp-d16
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#else
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.fpu softvfp
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#endif
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.thumb
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.text
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/*--------------------------------------------------------------------------*
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* Performs a context switch between two threads.
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*--------------------------------------------------------------------------*/
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.thumb_func
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.globl _port_switch
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_port_switch:
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push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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#if CORTEX_USE_FPU
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vpush {s16-s31}
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#endif
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str sp, [r1, #CONTEXT_OFFSET]
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#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) && \
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((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4))
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/* Workaround for ARM errata 752419, only applied if
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condition exists for it to be triggered.*/
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ldr r3, [r0, #CONTEXT_OFFSET]
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mov sp, r3
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#else
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ldr sp, [r0, #CONTEXT_OFFSET]
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#endif
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#if CORTEX_USE_FPU
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vpop {s16-s31}
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#endif
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pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
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/*--------------------------------------------------------------------------*
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* Start a thread by invoking its work function.
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*
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* Threads execution starts here, the code leaves the system critical zone
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* and then jumps into the thread function passed in register R4. The
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* register R5 contains the thread parameter. The function chThdExit() is
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* called on thread function return.
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*--------------------------------------------------------------------------*/
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.thumb_func
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.globl _port_thread_start
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_port_thread_start:
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl _dbg_check_unlock
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#endif
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#if CH_DBG_STATISTICS
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bl _stats_stop_measure_crit_thd
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#endif
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#if CORTEX_SIMPLIFIED_PRIORITY
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cpsie i
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#else
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movs r3, #0 /* CORTEX_BASEPRI_DISABLED */
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msr BASEPRI, r3
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#endif
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mov r0, r5
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blx r4
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#if defined(_CHIBIOS_RT_CONF_)
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movs r0, #0 /* MSG_OK */
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bl chThdExit
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#endif
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#if defined(_CHIBIOS_NIL_CONF_)
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mov r3, #0
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bl chSysHalt
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#endif
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/*--------------------------------------------------------------------------*
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* Post-IRQ switch code.
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*
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* Exception handlers return here for context switching.
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*--------------------------------------------------------------------------*/
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.thumb_func
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.globl _port_switch_from_isr
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_port_switch_from_isr:
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#if CH_DBG_STATISTICS
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bl _stats_start_measure_crit_thd
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#endif
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl _dbg_check_lock
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#endif
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bl chSchDoReschedule
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl _dbg_check_unlock
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#endif
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#if CH_DBG_STATISTICS
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bl _stats_stop_measure_crit_thd
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#endif
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.globl _port_exit_from_isr
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_port_exit_from_isr:
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#if CORTEX_SIMPLIFIED_PRIORITY
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movw r3, #:lower16:SCB_ICSR
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movt r3, #:upper16:SCB_ICSR
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mov r2, ICSR_PENDSVSET
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str r2, [r3, #0]
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cpsie i
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#else /* !CORTEX_SIMPLIFIED_PRIORITY */
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svc #0
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#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
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.L1: b .L1
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#endif /* !defined(__DOXYGEN__) */
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/** @} */
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