282 lines
8.7 KiB
C
282 lines
8.7 KiB
C
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/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file QUADSPIv1/hal_qspi_lld.h
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* @brief STM32 QSPI subsystem low level driver header.
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*
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* @addtogroup QSPI
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* @{
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*/
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#ifndef HAL_QSPI_LLD_H
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#define HAL_QSPI_LLD_H
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#if (HAL_USE_QSPI == TRUE) || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name QSPI capabilities
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* @{
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*/
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#define QSPI_SUPPORTS_MEMMAP TRUE
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/** @} */
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/**
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* @name DCR register options
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* @{
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*/
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#define STM32_DCR_CK_MODE (1U << 0U)
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#define STM32_DCR_CSHT_MASK (7U << 8U)
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#define STM32_DCR_CSHT(n) ((n) << 8U)
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#define STM32_DCR_FSIZE_MASK (31U << 16U)
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#define STM32_DCR_FSIZE(n) ((n) << 16U)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief QUADSPI1 driver enable switch.
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* @details If set to @p TRUE the support for QUADSPI1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_QSPI_USE_QUADSPI1) || defined(__DOXYGEN__)
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#define STM32_QSPI_USE_QUADSPI1 FALSE
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#endif
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/**
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* @brief QUADSPI1 prescaler setting.
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* @note This is the prescaler divider value 1..256. The maximum frequency
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* varies depending on the STM32 model and operating conditions,
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* find the details in the data sheet.
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*/
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#if !defined(STM32_QSPI_QUADSPI1_PRESCALER_VALUE) || defined(__DOXYGEN__)
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#define STM32_QSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif
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/**
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* @brief QUADSPI1 interrupt priority level setting.
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*/
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#if !defined(STM32_QSPI_QUADSPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_QSPI_QUADSPI1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief QUADSPI1 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_QSPI_QUADSPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_QSPI_QUADSPI1_DMA_PRIORITY 1
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#endif
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/**
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* @brief QUADSPI1 DMA interrupt priority level setting.
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*/
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#if !defined(STM32_QSPI_QUADSPI1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_QSPI_QUADSPI1_DMA_IRQ_PRIORITY 10
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#endif
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/**
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* @brief QUADSPI DMA error hook.
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*/
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#if !defined(STM32_QSPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_QSPI_DMA_ERROR_HOOK(qspip) osalSysHalt("DMA failure")
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#endif
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/**
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* @brief Enables a workaround for a STM32L476 QUADSPI errata.
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* @details The document DM00111498 states: "QUADSPI_BK1_IO1 is always an
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* input when the command is sent in dual or quad SPI mode".
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* This workaround makes commands without address or data phases
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* to be sent as alternate bytes.
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*/
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#if !defined(STM32_USE_STM32_D1_WORKAROUND) || defined(__DOXYGEN__)
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#define STM32_USE_STM32_D1_WORKAROUND TRUE
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if STM32_QSPI_USE_QUADSPI1 && !STM32_HAS_QUADSPI1
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#error "QUADSPI1 not present in the selected device"
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#endif
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#if !STM32_QSPI_USE_QUADSPI1
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#error "QSPI driver activated but no QUADSPI peripheral assigned"
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#endif
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#if STM32_QSPI_USE_QUADSPI1 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_QSPI_QUADSPI1_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to QUADSPI1"
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#endif
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#if STM32_QSPI_USE_QUADSPI1 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_QSPI_QUADSPI1_DMA_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to QUADSPI1 DMA"
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#endif
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#if STM32_QSPI_USE_QUADSPI1 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_QSPI_QUADSPI1_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to QUADSPI1"
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#endif
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#if (STM32_QSPI_QUADSPI1_PRESCALER_VALUE < 1) || \
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(STM32_QSPI_QUADSPI1_PRESCALER_VALUE > 256)
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#error "STM32_QSPI_QUADSPI1_PRESCALER_VALUE not within 1..256"
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#endif
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/* The following checks are only required when there is a DMA able to
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reassign streams to different channels.*/
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#if STM32_ADVANCED_DMA
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/* Check on the presence of the DMA streams settings in mcuconf.h.*/
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#if STM32_QSPI_USE_QUADSPI1 && !defined(STM32_QSPI_QUADSPI1_DMA_STREAM)
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#error "QUADSPI1 DMA stream not defined"
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#endif
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/* Check on the validity of the assigned DMA channels.*/
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#if STM32_QSPI_USE_QUADSPI1 && \
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!STM32_DMA_IS_VALID_ID(STM32_QSPI_QUADSPI1_DMA_STREAM, STM32_QUADSPI1_DMA_MSK)
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#error "invalid DMA stream associated to QUADSPI1"
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#endif
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#endif /* STM32_ADVANCED_DMA */
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type of a structure representing an QSPI driver.
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*/
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typedef struct QSPIDriver QSPIDriver;
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/**
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* @brief Type of a QSPI notification callback.
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*
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* @param[in] qspip pointer to the @p QSPIDriver object triggering the
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* callback
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*/
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typedef void (*qspicallback_t)(QSPIDriver *qspip);
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/**
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* @brief Driver configuration structure.
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*/
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typedef struct {
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/**
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* @brief Operation complete callback or @p NULL.
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*/
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qspicallback_t end_cb;
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/* End of the mandatory fields.*/
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/**
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* @brief DCR register initialization data.
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*/
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uint32_t dcr;
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} QSPIConfig;
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/**
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* @brief Structure representing an QSPI driver.
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*/
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struct QSPIDriver {
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/**
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* @brief Driver state.
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*/
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qspistate_t state;
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/**
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* @brief Current configuration data.
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*/
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const QSPIConfig *config;
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#if (QSPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)
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/**
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* @brief Waiting thread.
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*/
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thread_reference_t thread;
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#endif /* QSPI_USE_WAIT */
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#if (QSPI_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
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/**
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* @brief Mutex protecting the peripheral.
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*/
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mutex_t mutex;
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#endif /* QSPI_USE_MUTUAL_EXCLUSION */
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#if defined(QSPI_DRIVER_EXT_FIELDS)
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QSPI_DRIVER_EXT_FIELDS
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief Pointer to the QUADSPIx registers block.
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*/
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QUADSPI_TypeDef *qspi;
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/**
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* @brief QUADSPI DMA stream.
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*/
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const stm32_dma_stream_t *dma;
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/**
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* @brief QUADSPI DMA mode bit mask.
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*/
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uint32_t dmamode;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if (STM32_QSPI_USE_QUADSPI1 == TRUE) && !defined(__DOXYGEN__)
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extern QSPIDriver QSPID1;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void qspi_lld_init(void);
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void qspi_lld_start(QSPIDriver *qspip);
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void qspi_lld_stop(QSPIDriver *qspip);
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void qspi_lld_command(QSPIDriver *qspip, const qspi_command_t *cmdp);
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void qspi_lld_send(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, const uint8_t *txbuf);
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void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, uint8_t *rxbuf);
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#if QSPI_SUPPORTS_MEMMAP == TRUE
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void qspi_lld_map_flash(QSPIDriver *qspip,
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const qspi_command_t *cmdp,
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uint8_t **addrp);
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void qspi_lld_unmap_flash(QSPIDriver *qspip);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_QSPI */
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#endif /* HAL_QSPI_LLD_H */
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/** @} */
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