200 lines
6.1 KiB
C
200 lines
6.1 KiB
C
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/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file GPIOv3/hal_pal_lld.c
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* @brief STM32 PAL low level driver code.
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*
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* @addtogroup PAL
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#if defined(STM32L4XX)
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#define AHB2_EN_MASK STM32_GPIO_EN_MASK
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#define AHB2_LPEN_MASK 0
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#else
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#error "missing or unsupported platform for GPIOv3 PAL driver"
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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static void initgpio(stm32_gpio_t *gpiop, const stm32_gpio_setup_t *config) {
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gpiop->OTYPER = config->otyper;
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gpiop->ASCR = config->ascr;
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gpiop->OSPEEDR = config->ospeedr;
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gpiop->PUPDR = config->pupdr;
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gpiop->ODR = config->odr;
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gpiop->AFRL = config->afrl;
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gpiop->AFRH = config->afrh;
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gpiop->MODER = config->moder;
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gpiop->LOCKR = config->lockr;
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief STM32 I/O ports configuration.
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* @details Ports A-D(E, F, G, H) clocks enabled.
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*
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* @param[in] config the STM32 ports configuration
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*
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* @notapi
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*/
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void _pal_lld_init(const PALConfig *config) {
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/*
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* Enables the GPIO related clocks.
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*/
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#if defined(STM32L4XX)
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RCC->AHB2ENR |= AHB2_EN_MASK;
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#endif
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/*
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* Initial GPIO setup.
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*/
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#if STM32_HAS_GPIOA
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initgpio(GPIOA, &config->PAData);
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#endif
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#if STM32_HAS_GPIOB
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initgpio(GPIOB, &config->PBData);
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#endif
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#if STM32_HAS_GPIOC
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initgpio(GPIOC, &config->PCData);
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#endif
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#if STM32_HAS_GPIOD
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initgpio(GPIOD, &config->PDData);
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#endif
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#if STM32_HAS_GPIOE
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initgpio(GPIOE, &config->PEData);
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#endif
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#if STM32_HAS_GPIOF
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initgpio(GPIOF, &config->PFData);
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#endif
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#if STM32_HAS_GPIOG
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initgpio(GPIOG, &config->PGData);
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#endif
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#if STM32_HAS_GPIOH
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initgpio(GPIOH, &config->PHData);
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#endif
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#if STM32_HAS_GPIOI
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initgpio(GPIOI, &config->PIData);
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#endif
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#if STM32_HAS_GPIOJ
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initgpio(GPIOJ, &config->PJData);
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#endif
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#if STM32_HAS_GPIOK
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initgpio(GPIOK, &config->PKData);
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#endif
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}
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/**
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* @brief Pads mode setup.
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* @details This function programs a pads group belonging to the same port
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* with the specified mode.
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* @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum
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* speed.
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*
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* @param[in] port the port identifier
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* @param[in] mask the group mask
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* @param[in] mode the mode
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*
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* @notapi
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*/
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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iomode_t mode) {
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uint32_t moder = (mode & PAL_STM32_MODE_MASK) >> 0;
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uint32_t otyper = (mode & PAL_STM32_OTYPE_MASK) >> 2;
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uint32_t ospeedr = (mode & PAL_STM32_OSPEED_MASK) >> 3;
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uint32_t pupdr = (mode & PAL_STM32_PUPDR_MASK) >> 5;
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uint32_t altr = (mode & PAL_STM32_ALTERNATE_MASK) >> 7;
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uint32_t ascr = (mode & PAL_STM32_ASCR_MASK) >> 11;
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uint32_t lockr = (mode & PAL_STM32_LOCKR_MASK) >> 12;
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uint32_t bit = 0;
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while (true) {
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if ((mask & 1) != 0) {
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uint32_t altrmask, m1, m2, m4;
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altrmask = altr << ((bit & 7) * 4);
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m1 = 1 << bit;
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m2 = 3 << (bit * 2);
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m4 = 15 << ((bit & 7) * 4);
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port->OTYPER = (port->OTYPER & ~m1) | otyper;
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port->ASCR = (port->ASCR & ~m1) | ascr;
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port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr;
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port->PUPDR = (port->PUPDR & ~m2) | pupdr;
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if ((mode & PAL_STM32_MODE_MASK) == PAL_STM32_MODE_ALTERNATE) {
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/* If going in alternate mode then the alternate number is set
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before switching mode in order to avoid glitches.*/
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if (bit < 8)
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port->AFRL = (port->AFRL & ~m4) | altrmask;
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else
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port->AFRH = (port->AFRH & ~m4) | altrmask;
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port->MODER = (port->MODER & ~m2) | moder;
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}
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else {
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/* If going into a non-alternate mode then the mode is switched
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before setting the alternate mode in order to avoid glitches.*/
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port->MODER = (port->MODER & ~m2) | moder;
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if (bit < 8)
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port->AFRL = (port->AFRL & ~m4) | altrmask;
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else
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port->AFRH = (port->AFRH & ~m4) | altrmask;
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}
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port->LOCKR = (port->LOCKR & ~m1) | lockr;
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}
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mask >>= 1;
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if (!mask)
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return;
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otyper <<= 1;
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ospeedr <<= 2;
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pupdr <<= 2;
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moder <<= 2;
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bit++;
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}
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}
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#endif /* HAL_USE_PAL */
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/** @} */
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