nrf24l01p: added CW test mode
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10f4015583
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f7fd71aaf2
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@ -404,6 +404,29 @@ void nrf_off() {
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); // Most important: no R_CONFIG_PWR_UP
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); // Most important: no R_CONFIG_PWR_UP
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};
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};
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void nrf_startCW() {
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// Enable SPI correctly
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sspInit(0, sspClockPolarity_Low, sspClockPhase_RisingEdge);
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// Enable CS & CE pins
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gpioSetDir(RB_SPI_NRF_CS, gpioDirection_Output);
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gpioSetPullup(&RB_SPI_NRF_CS_IO, gpioPullupMode_Inactive);
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gpioSetDir(RB_NRF_CE, gpioDirection_Output);
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gpioSetPullup(&RB_NRF_CE_IO, gpioPullupMode_PullUp);
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CE_LOW();
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// Setup for nrf24l01+
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// power up takes 1.5ms - 3.5ms (depending on crystal)
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CS_LOW();
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nrf_write_reg(R_CONFIG, R_CONFIG_PWR_UP);
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delayms(2);
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nrf_write_reg(R_RF_SETUP, R_RF_SETUP_CONT_WAVE |
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R_RF_SETUP_PLL_LOCK |
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R_RF_SETUP_RF_PWR_3);
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nrf_write_reg(R_RF_CH, 81);
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CE_HIGH();
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}
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void nrf_check_reset(void){
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void nrf_check_reset(void){
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if(nrf_cmd_status(C_NOP) & R_STATUS_MAX_RT){
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if(nrf_cmd_status(C_NOP) & R_STATUS_MAX_RT){
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@ -85,7 +85,7 @@
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#define R_RF_CH_BITS 0x7f
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#define R_RF_CH_BITS 0x7f
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//RF_SETUP register definitions
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//RF_SETUP register definitions
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#define R_RF_CONT_WAVE 0x80
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#define R_RF_SETUP_CONT_WAVE 0x80
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#define R_RF_SETUP_RF_DR_LOW 0x20
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#define R_RF_SETUP_RF_DR_LOW 0x20
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#define R_RF_SETUP_PLL_LOCK 0x10
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#define R_RF_SETUP_PLL_LOCK 0x10
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#define R_RF_SETUP_RF_DR_HIGH 0x08
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#define R_RF_SETUP_RF_DR_HIGH 0x08
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@ -139,6 +139,7 @@ char nrf_snd_pkt_crc_encr(int size, uint8_t * pkt, uint32_t const k[4]);
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void nrf_init() ;
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void nrf_init() ;
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void nrf_off() ;
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void nrf_off() ;
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void nrf_startCW();
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void nrf_cmd(uint8_t cmd);
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void nrf_cmd(uint8_t cmd);
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uint8_t nrf_cmd_status(uint8_t cmd);
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uint8_t nrf_cmd_status(uint8_t cmd);
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