Merge branch 'master' of github.com:r0ket/r0ket
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/*
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* geigerct.c
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*
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*
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* Created on: 11.08.2011
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* Author: Turbo J <turboj@web.de>
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*
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* Implements simple Geiger Counter
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* Counts rising edges on P3_0 = BUSINT
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* so you can directly connect the Geiger board
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* from http://mightyohm.com/blog/products/geiger-counter/
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*
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*/
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#include <sysinit.h>
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#include <string.h>
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#include "basic/basic.h"
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#include "basic/config.h"
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#include "lcd/render.h"
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#include "lcd/print.h"
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#include "usetable.h"
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// Liberated from ARM Cortex M3 CMSIS core_cm3.h
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// The processor definition headers for R0ket are incomplete :-/
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#define __I
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#define __IO volatile
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typedef struct {
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__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */
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__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */
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__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */
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__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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__IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
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__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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__IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
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__IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */
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__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
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__IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */
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__IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */
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__IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
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__I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
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__I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
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__I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
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__I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
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__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */
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} SCB_Type;
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#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
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#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
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#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
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uint32_t VectorTableInRAM[73] __attribute__ ((aligned(1024))); // VTOR needs 1024 Byte alignment, see UM10375.PDF
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void (*orig_handler)(void); // original EINT3 handler
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void TIMER32_0_IRQHandler(void);
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// Remember: ram() must be the first function, place all other code AFTER
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// because the Implementer seem not to know how to use section attributes
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static void mainloop();
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void ram(void) {
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uint8_t button;
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uint32_t LEDs;
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// populate my Vector table
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memcpy(VectorTableInRAM, 0, sizeof(VectorTableInRAM));
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orig_handler = (void*) VectorTableInRAM[TIMER_32_0_IRQn + 16];
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VectorTableInRAM[TIMER_32_0_IRQn + 16] = (uint32_t) &TIMER32_0_IRQHandler;
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// HACK: use RAM vector table to implement own IRQ handler
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SCB->VTOR = (uint32_t) &VectorTableInRAM[0];
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// TODO add DMB() here, as VTOR updates are NOT effective immediately
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//
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NVIC_EnableIRQ(TIMER_32_0_IRQn);
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/* Enable the clock for CT32B0 */
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SCB_SYSAHBCLKCTRL |= (SCB_SYSAHBCLKCTRL_CT32B0);
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TMR_TMR32B0MR0 = (72E6/5E3)/2;
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TMR_TMR32B0MCR = (TMR_TMR32B0MCR_MR0_INT_ENABLED | TMR_TMR32B0MCR_MR0_RESET_ENABLED);
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TMR_TMR32B0TCR = TMR_TMR32B0TCR_COUNTERENABLE_ENABLED;
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mainloop();
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NVIC_DisableIRQ(TIMER_32_0_IRQn);
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TMR_TMR32B0TCR = TMR_TMR32B0TCR_COUNTERENABLE_DISABLED;
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// restore VTOR
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SCB->VTOR = 0;
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//TODO DMB(); Cortex Manual suggests DMB after setting VTOR
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// not really needed in this case
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}
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void TIMER32_0_IRQHandler(void)
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{
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TMR_TMR32B0IR = TMR_TMR32B0IR_MR0;
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static int time=0;
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if (time==0){time=1;} else {time=0;}
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gpioSetValue (RB_LED2, time);
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gpioSetValue (RB_SPI_SS3, time);
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}
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static void mainloop(void) {
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int dx=0;
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int dy=0;
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static uint32_t ctr=0;
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ctr++;
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setExtFont(GLOBAL(nickfont));
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dx=DoString(0,0,GLOBAL(nickname));
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dx=(RESX-dx)/2;
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if(dx<0)
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dx=0;
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dy=(RESY-getFontHeight())/2;
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lcdClear();
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lcdSetPixel(1,1,1);
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DoString(dx,dy,GLOBAL(nickname));
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lcdRefresh();
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while(getInputRaw()==BTN_NONE){
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delayms_queue_plus(10,0);
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};
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return;
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}
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