110 lines
5.3 KiB
C
110 lines
5.3 KiB
C
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/***************************************************************
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*
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* OpenBeacon.org - opcode & register definitions for nRF24L01
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*
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* Copyright 2007 Milosch Meriac <meriac@openbeacon.de>
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*
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* provides a nice set of defines to work properly with the
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* nRF24L01 CPU
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*
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***************************************************************
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; version 2.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef NRF_HW_H
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#define NRF_HW_H
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//********************************************************************************************************************//
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// SPI(nRF24L01) commands
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#define READ_REG 0x00 // Define read command to register
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#define WRITE_REG 0x20 // Define write command to register
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#define RD_RX_PLOAD 0x61 // Define RX payload register address
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#define WR_TX_PLOAD 0xA0 // Define TX payload register address
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#define FLUSH_TX 0xE1 // Define flush TX register command
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#define FLUSH_RX 0xE2 // Define flush RX register command
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#define REUSE_TX_PL 0xE3 // Define reuse TX payload register command
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#define OP_NOP 0xFF // Define No Operation, might be used to read status register
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#define ACTIVATE 0x50 // ACTIVATE additional features
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#define R_RX_PL_WID 0x60 // Define Read RX-payload width command
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#define W_ACK_PAYLOAD 0xA8 // Write payload to be used in ACK packet on pipe PPP
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#define W_TX_PAYLOAD_NOACK 0xB0 // Used in TX mode, Disable AUTOACK on this specific packet
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//********************************************************************************************************************//
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// SPI(nRF24L01) registers(addresses)
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#define CONFIG 0x00 // 'Config' register address
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#define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address
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#define EN_RXADDR 0x02 // 'Enabled RX addresses' register address
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#define SETUP_AW 0x03 // 'Setup address width' register address
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#define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address
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#define RF_CH 0x05 // 'RF channel' register address
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#define RF_SETUP 0x06 // 'RF setup' register address
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#define STATUS 0x07 // 'Status' register address
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#define OBSERVE_TX 0x08 // 'Observe TX' register address
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#define CD 0x09 // 'Carrier Detect' register address
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#define RX_ADDR_P0 0x0A // 'RX address pipe0' register address
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#define RX_ADDR_P1 0x0B // 'RX address pipe1' register address
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#define RX_ADDR_P2 0x0C // 'RX address pipe2' register address
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#define RX_ADDR_P3 0x0D // 'RX address pipe3' register address
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#define RX_ADDR_P4 0x0E // 'RX address pipe4' register address
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#define RX_ADDR_P5 0x0F // 'RX address pipe5' register address
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#define TX_ADDR 0x10 // 'TX address' register address
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#define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address
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#define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address
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#define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address
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#define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address
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#define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address
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#define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address
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#define FIFO_STATUS 0x17 // 'FIFO Status Register' register address
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#define FEATURE 0x1D // Additional features register, needed to enable the additional commands
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//********************************************************************************************************************//
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// SPI(nRF24L01) registers(bitmasks)
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#define ERX_P0 0x01 // Enable Pipe 0 (register EN_RXADDR)
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#define ERX_P1 0x02 // Enable Pipe 1 (register EN_RXADDR)
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#define ERX_P2 0x04 // Enable Pipe 2 (register EN_RXADDR)
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#define ERX_P3 0x08 // Enable Pipe 3 (register EN_RXADDR)
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#define ERX_P4 0x10 // Enable Pipe 4 (register EN_RXADDR)
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#define ERX_P5 0x20 // Enable Pipe 5 (register EN_RXADDR)
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//********************************************************************************************************************//
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// 'Config' register mask bits
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#define NRF_CONFIG_PRIM_RX 0x01
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#define NRF_CONFIG_PWR_UP 0x02
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#define NRF_CONFIG_CRCO 0x04
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#define NRF_CONFIG_EN_CRC 0x08
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#define NRF_CONFIG_MASK_MAX_RT 0x10
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#define NRF_CONFIG_MASK_TX_DS 0x20
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#define NRF_CONFIG_MASK_RX_DR 0x40
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#define NRF_CONFIG_MASK_IRQS (NRF_CONFIG_MASK_MAX_RT|NRF_CONFIG_MASK_TX_DS|NRF_CONFIG_MASK_RX_DR)
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#define MASK_RX_DR_FLAG 0x40
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#define MASK_TX_DS_FLAG 0x20
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#define MASK_MAX_RT_FLAG 0x10
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#define MASK_IRQ_FLAGS (MASK_MAX_RT_FLAG|MASK_TX_DS_FLAG|MASK_RX_DR_FLAG)
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#define FIFO_RX_EMPTY 0x01
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#define FIFO_RX_FULL 0x02
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#define FIFO_TX_EMPTY 0x10
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#define FIFO_TX_FULL 0x20
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#define FIFO_TX_REUSE 0x40
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#define NRF_MIN_MAC_SIZE 3
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#define NRF_MAX_MAC_SIZE 5
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#define NRF_MAX_BUFFER_SIZE 32
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#endif /*NRF_HW_H */
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